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Datasheet File OCR Text:

Advance Information
This document contains information on a product under development. The parametric information contains target parameters that are subject to change.
BT848/848A/849A
Single-Chip Video Capture for PCI
BT848 is a complete, low cost single-chip solution for analog NTSC/PAL/SECAM video capture on the PCI bus. As a bus master, BT848 does not require any local memory buffers to store video pixel data which significantly minimizes the hardware cost for this architecture. BT848 takes advantage of the PCI-based system's high bandwidth and inherent multimedia capability. It is designed to be interoperable with any other PCI multimedia device at the component or board level, thus enabling video capture and overlay capability to be added to PCI systems in a modular fashion at low cost. The BT848 solution is independent of the PCI system bus topology and may be used in a variety of system bus organizations: directly on a motherboard planar bus, on a card for a planar or secondary bus. The BT848A/849A are fully backward compatible enhancements to the BT848. The BT848A and 849A both include all the functionality of the BT848, while adding support for peaking, single crystal operation, and digital camera support.
Distinguishing Features
* Fully PCI Rev. 2.1 compliant * Auxiliary GPIO data port and video data port * Supports image resolutions up to 768x576 (full PAL resolution) * Supports complex clipping of video source * Zero wait state PCI burst writes * Field/frame masking support to throttle bandwidth to target * Multiple YCrCb and RGB pixel formats supported on output * Supports NTSC/SECAM/PAL analog input * Image size scalable down to icon using vertical & horizontal interpolation filtering * Multiple composite and S-video inputs * Supports different destinations for even and odd fields * Supports different color space/scaling factors for even and odd fields * Support for mapping of video to 225 color palette * VBI data capture for closed captioning, teletext and intercast data decoding
Functional Block Diagram
XTAL
MUXIN MUXOUT
Analog Mux
UltralockTM and Clock Generation
Video Timing Unit
IIC
JTAG
PCI I/F SYNCDET REFOUT AGC Horizontal, Vertical and Temporal Scaling Decimation LPF Pixel Format Conversion Target
Additional Features in BT848A/849A Only
* Supports peaking * Requires only one crystal * Digital camera support through GPIO port * Support for WST decode (Bt849A only)
YIN
40 MHz ADC
630 Byte FIFO Luma-Chroma Separation and Chroma Demod Digital Camera Input (BT848A/849A) and GPIO Port
Initiator DMA Controller
CIN
40 MHz ADC
Applications
* * * * * * * PC TV Intercast receiver Desktop video phone Motion video capture Still frame capture Teletext/Intertext VBI data services capture
Brooktree
(R)
Brooktree Division * Rockwell Semiconductor Systems, Inc. * 9868 Scranton Road * San Diego, CA 92121-3707 619-452-7580 * 1-800-2-BT-APPS * FAX: 619-452-1249 * Internet: apps@brooktree.com * L848A_A
Ordering Information
Model Number BT848KPF BT848AKPF Bt849AKPF Package 160-pin PQFP 160-pin PQFP 160-pin PQFP Ambient Temperature Range 0C to +70C 0C to +70C 0C to +70C
Copyright (c) 1997 Brooktree Corporation. All rights reserved. Print date: February 1997 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree Corporation. Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from such improper use or sale. Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
TABLE OF CONTENTS
List Of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Video Capture Over PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supports Intel IntercastTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BT848A Analog Video and Digital Camera Capture Over the PCI Bus . . . . . . . . . . . . DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UltraLock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vertical Blanking Interval Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 2 4 5 5 5 5 6 6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operation Principles of UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Composite Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Y/C Separation and Chroma Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Video Scaling, Cropping, and Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Horizontal and Vertical Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peaking (BT848A and Bt849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 24 26 26 28 30 31
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TABLE OF CONTENTS
Single-Chip Video Capture for PCI
Video Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
The Hue Adjust Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Contrast Adjust Register (CONTRAST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Saturation Adjust Registers (SAT_U, SAT_V) . . . . . . . . . . . . . . . . . . . . . . . . . . The Brightness Register (BRIGHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 33
Automatic Chrominance Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low Color Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VBI Data Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Video Data Format Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pixel Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Control Code Status Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YCrCb to RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gamma Correction Removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YCrCb Sub-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Input/Output Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RISC Program Setup and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RISC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Over-run Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Data Stream Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 41 41 41 42 43 44 45 45 48 49 49 55 56 56 58
Video and Control Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autodetection of NTSC or PAL/SECAM Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Gain Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Crystal Operation (BT848A/849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2X Oversampling and Input Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 60 60 60 60 60 64 65
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BT848/848A/849A
Single-Chip Video Capture for PCI
TABLE OF CONTENTS
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 General Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 GPIO SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Digital Video in Support (BT848A/849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 78 78
PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latch-up Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 80 80 80 80 81
Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Vendor and Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Command and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Revision ID and Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Base Address 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register . . . . . . . . . . . . . . . . . . . . . . 89 Local Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Input Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Temporal Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MSB Cropping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Vertical Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Vertical Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Horizontal Delay Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Horizontal Active Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Horizontal Scaling Register, Upper Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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TABLE OF CONTENTS
Single-Chip Video Capture for PCI
Horizontal Scaling Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Brightness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Luma Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Chroma (U) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Chroma (V) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Hue Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SC Loop Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Output Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Vertical Scaling Register, Upper Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Vertical Scaling Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Test Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 AGC Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Burst Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ADC Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Video Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Color Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Color Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Capture Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 VBI Packet Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 VBI Packet Size / Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PLL Reference Multiplier - PLL_F_LO (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . 111 PLL Reference Multiplier - PLL_F_HI (BT848A/849A only). . . . . . . . . . . . . . . . . . . . . 111 Integer- PLL-XCI (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Field Capture Counter-(FCAP) (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RISC Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RISC Program Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO and DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 GPIO Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO Registered Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I2C Data/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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TABLE OF CONTENTS
Control Register Digital Video In Support (BT848A/849A Only). . . . . . . . . . . . . . . 119
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Digital Video Signal Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Timing Generator Load Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Timing Generator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Luma Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chroma (V) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Chroma (U) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 HDELAY/HSCALE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ParametricInformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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LIST OF FIGURES
Single-Chip Video Capture for PCI
List Of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. BT848/848A/849A Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 BT848 Video Decoder and Scaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BT848/848A/849A Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UltraLock Behavior for NTSC Square Pixel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Y/C Separation and Chroma Demodulation for Composite Video . . . . . . . . . . . . . . . . . . 19 Y/C Separation Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Filtering and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Optional Horizontal Luma Low-Pass Filter Responses. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM) . . . . . . . . . . . . . . . . . . . . . . . . . 22 Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . 23 Combined Luma Notch and 2x Oversampling Filter Response . . . . . . . . . . . . . . . . . . . . 23 Peaking Filters (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Luma Peaking Filters with 2x Oversampling Filter and Luma Notch (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Effect of the Cropping and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Coring Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Regions of the Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 VBI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VBI Section Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Video Data Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data FIFO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 RISC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Example of BT848 Performing Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Luma and Chroma 2x Oversampling Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 GPIO SPI Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 GPIO SPI Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Video Timing in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Basic Timing Relationships for SPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 CCIR 656 or ByteStream Interface to Digital Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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LIST OF FIGURES
Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45.
The Relationship between SCL and SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 I2C Typical Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Example Ground Plane Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Optional Regulator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical Power and Ground Connection Diagram and Parts List . . . . . . . . . . . . . . . . . . . 82 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 GPIO Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 160-pin PQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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LIST OF TABLES
Single-Chip Video Capture for PCI
List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. PCI Video Decoder Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Descriptions Grouped by Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BT848 Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Video Input Formats Supported by the BT848 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register Values for Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Scaling Ratios for Popular Formats Using Frequency Values . . . . . . . . . . . . . . . . . . . . . . 28 Color Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Byte Swapping Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table of PCI Bus Access Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RISC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIFO Full/Almost Full Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Synchronous Pixel Interface (SPI) GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Pin Definition of GPIO Port When Using Digital Video-In Mode . . . . . . . . . . . . . . . . . . . . 73 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Clock Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 GPIO SPI Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Power Supply Current Parameters (BT848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . 128 JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Decoder Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 BT848 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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FUNCTIONAL DESCRIPTION
Functional Overview
Video Capture Over PCI Bus The BT848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video decoder, scaler, DMA controller, and PCI Bus master on a single device. BT848/848A/849A can place video data directly into host memory for video capture applications and into a target video display frame buffer for video overlay applications. As a PCI initiator, BT848/848A/849A can take control of the PCI bus as soon as it is available, thereby avoiding the need for on-board frame buffers. BT848/848A/849A contains a pixel data FIFO to decouple the high speed PCI bus from the continuous video data stream. Figure 1 shows a block diagram of the BT848/848A/849A, and Figure 2 shows a detailed block diagram of the decoder and scaler sections. The video data input may be scaled, color translated, and burst transferred to a target location on a field basis. This allows for simultaneous preview of one field and capture of the other field. Alternatively, BT848/848A/849A is able to capture both fields simultaneously or preview both fields simultaneously. The fields may be interlaced into memory or sent to separate field buffers. The Bt849A includes all the capability in the BT848A and adds support for WST decoding (the encoding method for European based Teletext). The Bt849A implements a significant amount of WST decoding in S/W ensuring a very low cost TV card for use in locations requiring Teletext See Table 1 for a comparison of the BT848/848A/849A. The BT848/848A/849A fully supports the Intel Intercast technology. Intel Intercast technology combines the rich programming of television and the exciting world of the Internet on your PC. Imagine watching a news broadcast and simultaneously getting a Web page providing a historical perspective. Or viewing a music video and ordering tickets on the Internet for the band's next appearance in your area. Or enjoying a favorite show and getting special web pages associated with that program. Now your PC can let you interact with television in all kinds of new and exciting ways.
Supports Intel IntercastTM
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FUNCTIONAL DESCRIPTION
Functional Overview
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 1. PCI Video Decoder Product Family BT848 Composite, S-Video multi-standard Video Decoder and PCI bus master Peaking, single crystal operation, digital camera support WST (Teletext) decoding support X BT848A X X Bt849A X X X
BT848A Analog Video and Digital Camera Capture Over the PCI Bus
The BT848A provides support for digital cameras. The BT848A includes a digital camera port providing the ability to perform digital capture when a BT848A is used in the development of a video board product. The BT848A is fully compatible with the BT848. The datasheet defines the registers and functionality required for implementing analog video capture support. In order to implement digital video interface, refer to the Digital Video section of the datasheet. Note the majority of the register settings are identical for both analog and digital video support. The Digital Video section identifies all changes, additional registers, all changes to the analog register setting that are required in order to support digital video. The BT848A can accept digital video from a multitude of sources including the Silicon Vision and Logitech video cameras. The digital stream is routed to the high quality down scaler and color adjustment processing. It is then bus mastered into system memory or displayed via the graphics frame buffer. BT848/848A/849A provides two DMA channels for the odd and even fields, each controlled by a pixel instruction list. This instruction list is created by the BT848 device driver and placed in the host memory. The instructions control the transfer of pixels to target memory locations on a byte resolution basis. Complex clipping can be accomplished by the instruction list, blocking the generation of PCI bus cycles for pixels that are not to be seen on the display. The DMA channels can be programmed on a field basis to deliver the video data in packed or planar format. In packed mode, YCrCb data is stored in a single continuous block of memory. In planar mode, the YCrCb data is separated into three streams which are burst to different target memory blocks. Having the video data in planar format is useful for applications where the data compression is accomplished via software and the CPU.
DMA Channels
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GPIO (Digital Video Input BT848A & Bt849A Only) Video Data Format Converter YCrCb 4:2:2, 4:1:1 Format CSC/Gamma MUX 8-Bit Dither Cb: 35x36 Cr: 35x36 # DWORDS Instruction Queue Video Decoder Video Scaler FIFOs Y: 70x36 DMA Controller PCI Initiator Address Generator FIFO Data MUX PCI Bus Local Registers Wr
(R)
Figure 1. BT848/848A/849A Detailed Block Diagram
L848A_A
GPIO I2C Master PCI Config Registers PCI Target Controller Interrupts
Analog Video
Instr
Data
AD MUX Rd Parity Generator
PCI Bus
FUNCTIONAL DESCRIPTION
Functional Overview
3
FUNCTIONAL DESCRIPTION
Functional Overview
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 2. BT848 Video Decoder and Scaler Block Diagram
SYNCDET(!)
MUXOUT
AGCCAP
REFOUT
MUX3(2)
MUX0
MUX1
MUX2
XT1O
XT0O
XT1I
AGC and Sync Detect
YREF+ YIN YREF-
Clocking
Y A/D
XT0I
Hue, Saturation, and Brightness Adjust
CLEVEL
CREF-
Notes: (1). BT848 only. (2). BT848A and Bt849A only.
PCI Bus Interface
BT848/848A/849A is designed to efficiently utilize the available 132 MB/s PCI bus. The 32-bit DWORDs are output on the PCI bus with the appropriate image data under the control of the DMA channels. The video stream consumes bus bandwidth with average data rates varying from 44 MB/s for full size 768x576 PAL RGB32, to 4.6 MB/s for NTSC CIF 320 x 240 RGB16, to 0.14 MB/s for NTSC ICON 80 x 60 8-bit mode. The pixel instruction stream for the DMA channels consumes a minimum of 0.1 MB/s. Achieving high performance throughput on PCI may be a problem with slow targets and long bus access latencies. The BT848/848A/849A provides the means for handling the bandwidth bottlenecks that sometimes occur depending on a particular system configuration. BT848/848A/849A's ability to gracefully degrade and to recover from FIFO overruns to the nearest pixel in real-time is the best possible solution to these system bottlenecks.
Chroma Demod
CIN
C A/D
CREF+
4
L848A_A
Horizontal and Vertical Filtering and Scaling
Oversampling Low-Pass Filter
Y/C Separation
Brooktree
To FIFO Input Data Formatter
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Functional Overview
UltraLock
The BT848/848A/849A employs a proprietary technique known as UltraLock to lock to the incoming analog video signal. It will always generate the required number of pixels per line from an analog source in which the line length can vary by as much as a few microseconds. UltraLock's digital locking circuitry enables the VideoStream decoders to quickly and accurately lock on to video signals, regardless of their source. Since the technique is completely digital, UltraLock can recognize unstable signals caused by VCR headswitches or any other deviation, and adapt the locking mechanism to accommodate the source. UltraLock uses nonlinear techniques which are difficult, if not impossible, to implement in genlock systems. And unlike linear techniques, it adapts the locking mechanism automatically. The BT848/848A/849A can reduce the video image size in both horizontal and vertical directions independently using arbitrarily selected scaling ratios. The X and Y dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal scaling is implemented with a six-tap interpolation filter while up to 5-tap interpolation is used for vertical scaling with a line store. The video image can be arbitrarily cropped by reducing the number of active scan lines and active horizontal pixels per line. The BT848/848A/849A supports a temporal decimation feature that reduces video bandwidth by allowing frames or fields to be dropped from a video sequence at fixed but arbitrarily selected intervals. Analog video signals are input to the BT848/848A/849A via a three-input multiplexer that can select between three composite source inputs or between two composite and a single S-video input source. When an S-video source is input to the BT848/848A/849A, the luma component is fed through the input analog multiplexer, and the chroma component is fed directly into the C input pin. An automatic gain control circuit enables the BT848 to compensate for non-standard amplitudes in the analog signal input. On the BT848A and Bt849A there is an additional mux input (providing a four-input multiplexer). The clock signal interface consists of two pairs of pins for crystal connection and two clock output pins. One pair of crystal pins is for connection to a 28.64 MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The other is for PAL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either fundamental or third harmonic crystals may be used. Alternatively, CMOS oscillators may be used. The BT848/848A/849A provides a 24-bit general purpose I/O bus. This interface can be used to input or output up to 24 general purpose I/O signals. Alternatively, the GPIO port can be used as a means to input or output video decoder data. For example, the BT848/848A/849A can input the video data from an external video decoder and bypass the BT848/848A/849A's internal video decoder block. Another application is to output the video decoder data from the BT848/848A/849A over the GPIO bus for use by external circuitry.
Scaling and Cropping
Input Interface
GPIO
Brooktree
(R)
L848A_A
5
FUNCTIONAL DESCRIPTION
Functional Overview
BT848/848A/849A
Single-Chip Video Capture for PCI
Vertical Blanking Interval Data Capture
BT848/848A/849A provides a complete solution for capturing and decoding Vertical Blanking Interval (VBI) data. The BT848/848A/849A can operate in a VBI Line Output Mode, in which the VBI data is only captured during select lines. This mode of operation enables concurrent capture of VBI lines containing ancillary data and normal video image data. In addition, the BT848/848A/849A supports a VBI Frame Output Mode, in which every line in the video frame is treated as if it was a VBI line. This mode of operation is designed for use with still frame capture/processing applications. The BT848/848A/849A provides a two-wire Inter-Integrated Circuit (I2C) interface. As an I2C master, BT848/848A/849A can program other devices on the video card, such as a TV tuner. Serial clock and data lines, SCL and SDA are used to transfer data at a rate of 100 Kbits/s.
I2C Interface
6
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Pin Descriptions
Table 2 provides a description of pin functions, grouped by common function, Table 3 is a list of pin names in pin-number order, and Figure 3 shows the pinout diagram.
NOTE:
Pins with alternate definitions on the BT848A and Bt849A are indicated by shading
Table 2. Pin Descriptions Grouped by Pin Function (1 of 6) Pin # Pin Name I/O Signal Description PCI Interface (50 pins) 11 CLK I Clock This input provides timing for all PCI transactions. All PCI signals except RST and INTA are sampled on the rising edge of CLK, and all other timing parameters are defined with respect to this edge. The BT848 supports a PCI clock of up to 33.333333 MHz. This input three-states all PCI signals asynchronous to the CLK signal. Agent granted bus. This input is used to select the BT848 during configuration read and write transactions. These three-state, bi-directional, I/O pins transfer both address and data information. A bus transaction consists of an address phase followed by one or more data phases for either read or write operations. The address phase is the clock cycle in which FRAME is first asserted. During the address phase, AD[31:0] contains a byte address for I/O operations and a DWORD address for configuration and memory operations. During data phases, AD[7:0] contains the least significant byte and AD[31:24] contains the most significant byte. Read data is stable and valid when TRDY is asserted and write data is stable and valid when IRDY is asserted. Data is transferred during the clocks when both TRDY and IRDY are asserted. These three-state, bi-directional, I/O pins transfer both bus command and byte enable information. During the address phase of a transaction, CBE[3:0] contain the bus command. During the data phase, CBE[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. CBE[3] refers to the most significant byte and CBE[0] refers to the least significant byte.
9 13 28 15-17, 20-24, 29-32, 35-38, 53-55, 58-62, 66-69, 72-75
RST GNT IDSEL AD[31:0]
I I I I/O
Reset Grant Initialization Device Select Address/Data
27, 39, 52, 65
CBE[3:0]
I/O
Bus Command/Byte Enables
Brooktree
(R)
L848A_A
7
FUNCTIONAL DESCRIPTION
Pin Descriptions
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 2. Pin Descriptions Grouped by Pin Function (2 of 6) Pin # 51 Pin Name PAR I/O I/O Signal Parity Description This three-state, bi-directional, I/O pin provides even parity across AD[31:0] and CBE[3:0]. This means that the number of 1's on PAR, AD[31:0], and CBE[3:0] equals an even number. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either TRDY is asserted on a read or IRDY is asserted on a write. Once valid, PAR remains valid until one clock after the completion of the current data phase. PAR and AD[31:0] have the same timing, but PAR is delayed by one clock. The target drives PAR for read data phases; the master drives PAR for address and write data phases. This sustained three-state signal is driven by the current master to indicate the beginning and duration of an access. FRAME is asserted to signal the beginning of a bus transaction. Data transfer continues throughout assertion. At deassertion, the transaction is in the final data phase. This sustained three-state signal indicates the bus master's readiness to complete the current data phase. IRDY is used in conjunction with TRDY. When both IRDY and TRDY are asserted, a data phase is completed on that clock. During a read, IRDY indicates when the initiator is ready to accept data. During a write, IRDY indicates when the initiator has placed valid data on AD[31:0]. Wait cycles are inserted until both IRDY and TRDY are asserted together. This sustained three-state signal indicates the target's readiness to complete the current data phase. IRDY is used in conjunction with TRDY. When both IRDY and TRDY are asserted, a data phase is completed on that clock. During a read, TRDY indicates when the target is presenting data. During a write, TRDY indicates when the target is ready to accept the data. Wait cycles are inserted until both IRDY and TRDY are asserted together. This sustained three-state signal indicates device selection. When actively driven, DEVSEL indicates the driving device has decoded its address as the target of the current access. This sustained three-state signal indicates the target is requesting the master to stop the current transaction. Report data parity error. Agent desires bus. This signal is an open drain interrupt output. Report address parity error. Open drain.
42
FRAME
I/O
Cycle Frame
43
IRDY
I/O
Initiator Ready
44
TRDY
I/O
Target Ready
45
DEVSEL
I/O
Device Select
46 49 14 8 50
STOP PERR REQ INTA SERR
I/O I/O O O O
Stop Parity Error Request Interrupt A System Error
See PCI Specification 2.1 for further documentation
8
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function (3 of 6) Pin # Pin Name I/O Signal Description General Purpose I/O (27 pins) 82-89, 92-99, 110-117 GPIO[23:0] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[9] GPIO[8] GPIO[7:0] I/O O O O O O O O O I I I General Purpose I/O Clkx1 Field Vactive Vsync Hactive Hsync Composite Active Composite Sync Vsync/Field Hsync Video Data Input at GPCLK = CLKX2 rate GP Interrupt GP Write Enable GP Clock 24 bits of programmable I/O. These pins are internally pulled up to VDDG. BT848A and Bt849A pin decoding when in digital video input and SPI mode.
119 118 108
GPINTR GPWE GPCLK
I I I/O
GP port requests an interrupt. Internally pulled up to VDDG. GP port write enable for registered inputs. Internally pulled up to VDDG. Video clock. Internally pulled up to VDDG. Input Stage (14 pins)
141 143 145 139 138 154 147
MUX0 MUX1 MUX2 MUXOUT YIN CIN SYNCDET
I I I O I I I
Analog composite video inputs to the on-chip input multiplexer. Used to select between three composite sources or two composite and one S-video source. Unused pins should be connected to ground. The analog video output of the 3 to 1 multiplexer. Must connect to the YIN pin. The analog composite or luma input to theY-ADC. The analog chroma input to the C-ADC. The sync stripper input used to generate timing information for the AGC circuit. Must be connected through a 0.1 F capacitor to the same source as the Y-ADC. A 1 M bleeder resistor should be connected to ground. In the BT848A and Bt849A the SYNCDET is not required and is used as a fourth mux input. Analog composite video inputs to the on-chip input multiplexer. Used to select between three composite sources or two composite and one S-video source. Unused pins should be connected to ground. The AGC time constant control capacitor node. Must be connected to a 0.1 F capacitor to ground.
MUX3
I
131
AGCCAP
A
Brooktree
(R)
L848A_A
9
FUNCTIONAL DESCRIPTION
Pin Descriptions
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 2. Pin Descriptions Grouped by Pin Function (4 of 6) Pin # 133 Pin Name REFOUT REFOUT I/O O O Signal Description Output of the AGC which drives the YREF+ and CREF+ pins. In the BT848Aand Bt849A, the external 30 K, 30 K, and 2 K resistors are not required. However, the 0.1 F capacitor ground to GND is still needed (see Figure 25). The top of the reference ladder of the Y-ADC. This should be connected to REFOUT. The bottom of the reference ladder of the Y-ADC. This should be connected to analog ground (AGND). The top of the reference ladder of the C-ADC. This should be connected to REFOUT. The bottom of the reference ladder of the C-ADC. This should be connected to analog ground (AGND). An input to provide the DC level reference for the C-ADC. This voltage should be one half of CREF+. In the BT848A and Bt849A, this input is internally generated. No external components are required. I2C Interface (2 pins) 78 79 SCL SDA I/O I/O Serial Clock Serial Data Bus clock, output open drain. Bit Data or Acknowledge, output open drain.
137 150 151 157 158
YREF+ YREF- CREF+ CREF- CLEVEL CLEVEL
I I I I I I
Video Timing Clock Interface (5 pins) 102 103 XT0I XT0O A A Clock Zero pins. A 28.636363 MHz (8*Fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to XT0I. CMOS level inputs must be used. This clock source is selected for NTSC input sources. When the chip is configured to decode PAL but not NTSC (and therefore only one clock source is needed), the 35.468950 MHz source is connected to this port (XT0). In the BT848A and Bt849A, this is the only clock source required to decode all video formats. If only one source is used the frequency must be 28.636363 MHz (50 ppm) and a series resistor must be added to the layout. Alternatively, the BT848A and Bt849A may be configured exactly as the BT848 (using 28.636363 and 35.468950 MHz sources). Clock One pins. A 35.468950 MHz (8*Fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to XT1I. CMOS level inputs must be used. This clock source is selected for PAL input sources. If either NTSC or PAL is being decoded, and therefore only XT0I and XT0O are connected to a crystal, XT1I should be tied either high or low, and XT1O must be left floating.
XT0I XT0O
A A
105 106
XT1I XT1O
A A
10
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function (5 of 6) Pin # 104 Pin Name NUMXTAL I/O I Signal Description Crystal Format Pin. This pin is set to indicate whether one or two crystals are present so that the BT848 can select XT1 or XT0 as the default in auto format mode. A logical zero on this pin indicates one crystal is present. A logical one indicates two crystals are present. This pin is internally pulled up to VDDG. JTAG (5 pins) 3 TCK I Test clock. Used to synchronize all JTAG test structures. When JTAG operations are not being performed, this pin must be driven to a logical low. Test Mode Select. JTAG input pin whose transitions drive the JTAG state machine through its sequences. When JTAG operations are not being performed, this pin must be left floating or tied high. Test Data Input. JTAG pin used for loading instructions to the TAP controller or for loading test vector data for boundary-scan operation. When JTAG operations are not being performed, this pin must be left floating or tied high. Test Data Output. JTAG pin used for verifying test results of all JTAG sampling operations. This output pin is active for certain JTAG operations and will be three-stated at all other times. Test Reset. JTAG pin used to initialize the JTAG controller. This pin is tied low for normal device operation. When pulled high, the JTAG controller is ready for device testing. Note: Not all PCs drive the PCI bus TRST pin. In these computers, if the TRST pin on the BT848 board is connected to TRST on the PCI bus (which is not driven) the BT848 may power up in an undefined state. In these designs, the TRST pin on the BT848 card must be tied low (disabling JTAG). Power & Ground (57 pins) 1, 18, 40, 63, 81, 101, 120 130, 134, 136, 148, 152, 156 VDD +5V P Power supply for digital circuitry. All VDD pins must be connected together as close to the device as possible. A 0.1 F capacitor should be connected between each group of VDD pins and the ground plane as close to the device as possible. Power supply for analog circuitry. All VAA pins and VPOS must be connected together as close to the device as possible. A 0.1 F ceramic capacitor should be connected between each group of VAA pins and the ground plane as close to the device as possible. Power supply for PCI bus signals. A 0.1 F ceramic capacitor should be connected between the VDDP pins and the ground plane as close to the device as possible.
5
TMS
I
7
TDI
I
6
TDO
O
2
TRST
I
VAA +5V VPOS +5V
P
10, 25, 33, 47, 56, 70, 76
VDDP PCI VIO
P
Brooktree
(R)
L848A_A
11
FUNCTIONAL DESCRIPTION
Pin Descriptions
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 2. Pin Descriptions Grouped by Pin Function (6 of 6) Pin # 90, 109, 123 12, 19, 26, 34, 41, 48, 57, 64, 71, 77, 80, 91, 100, 107, 121, 122, 160 132, 135, 140, 142, 144, 146, 149, 153, 155, 159 4 Pin Name VDDG +5V I/O P Signal Description Power supply for GPIO port signals. A 0.1 F ceramic capacitor should be connected between the VDDG pins and the ground plane as close to the device as possible. Ground for digital circuitry. All GND pins must be connected together as close to the device as possible.
GND
G
AGND, VNEG
G
Ground for analog circuitry. All AGND pins and VNEG must be connected together as close to the device as possible.
PVREF
A
This pin should be connected to GND (this reference signal may be connected to the +3.3 V pin on the PCI bus, even if the PCI bus does not supply 3.3 V). No connect Reserved These pins are remapped on the BT848A and Bt849A to provide the same functionality as on the BT848 but on a different pin.
124-129
N/C GPX[5:0] I/O
Remapped from GPIO [5:0]
I/O Column Legend: I = Digital Input O = Digital Output I/O = Digital Bidirectional A = Analog G = Ground P = Power
12
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Assignments
Pin Assignments
Figure 3. BT848/848A/849A Pinout Diagram
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND AGND CLEVEL CREF- VAA AGND CIN AGND VAA CREF+ YREF- AGND VAA SYNCDET (MUX3) AGND MUX2 AGND MUX1 AGND MUX0 AGND MUXOUT YIN YREF+ VAA AGND VAA REFOUT VNEG AGCCAP VPOS N/C (GPX0) N/C (GPX1) N/C (GPX2) N/C (GPX3) N/C (GPX4) N/C (GPX5) VDDG GND GND
VDD TRST TCK PVREF TMS TDO TDI INTA RST VDDP CLK GND GNT REQ AD[31] AD[30] AD[29] VDD GND AD[28] AD[27] AD[26] AD[25] AD[24] VDDP GND CBE[3] IDSEL AD[23] AD[22] AD[21] AD[20] VDDP GND AD[19] AD[18] AD[17] AD[16] CBE[2] VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
BT848/848A/849A
VDD GPINTR GPWE GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] VDDG GPCLK GND XT1O XT1I NUMXTAL XT0O XT0I VDD GND GPIO[8] (HSYNC) GPIO[9] (VSYNC/FIELD) GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GND VDDG GPIO[16] (Composite SYNC) GPIO[17] (Composite ACTIVE) GPIO[18] (HSYNC) GPIO[19] (HACTIVE) GPIO[20] (VSYNC) GPIO[21] (VACTIVE) GPIO[22] (FIELD) GPIO[23] (CLKX1) VDD
Note: BT848A and Bt849A pin alternate definitions indicated in ().
Brooktree
GND FRAME IRDY TRDY DEVSEL STOP VDDP GND PERR SERR PAR CBE[1] AD[15] AD[14] AD[13] VDDP GND AD[12] AD[11] AD[10] AD[9] AD[8] VDD GND CBE[0] AD[7] AD[6] AD[5] AD[4] VDDP GND AD[3] AD[2] AD[1] AD[0] VDDP GND SCL SDA GND
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
(R)
L848A_A
13
FUNCTIONAL DESCRIPTION
Pin Assignments
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 3. BT848 Pin List Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name VDD TRST TCK PVREF TMS TDO TDI INTA RST VDDP CLK GND GNT REQ AD[31] AD[30] AD[29] VDD GND AD[28] AD[27] AD[26] AD[25] AD[24] VDDP GND CBE[3] IDSEL AD[23] AD[22] AD[21] AD[20] Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name VDDP GND AD[19] AD[18] AD[17] AD[16] CBE[2] VDD GND FRAME IRDY TRDY DEVSEL STOP VDDP GND PERR SERR PAR CBE[1] AD[15] AD[14] AD[13] VDDP GND AD[12] AD[11] AD[10] AD[9] AD[8] VDD GND Pin # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name CBE[0] AD[7] AD[6] AD[5] AD[4] VDDP GND AD[3] AD[2] AD[1] AD[0] VDDP GND SCL SDA GND VDD GPIO[23](1) GPIO[22](1) GPIO[21](1) GPIO[20](1) GPIO[19](1) GPIO[18](1) GPIO[17](1) GPIO[16](1) VDDG GND GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] Pin # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name GPIO[10] GPIO[9](1) GPIO[8](1) GND VDD XT0I XT0O NUMXTAL XT1I XT1O GND GPCLK VDDG GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] GPWE GPINTR VDD GND GND VDDG N/C(1) N/C(1) N/C(1) N/C(1) N/C(1) Pin # 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name N/C(1) VPOS AGCCAP VNEG REFOUT VAA AGND VAA YREF+ YIN MUXOUT AGND MUX0 AGND MUX1 AGND MUX2 AGND SYNCDET(1) VAA AGND YREF- CREF+ VAA AGND CIN AGND VAA CREF- CLEVEL AGND GND
Notes: (1). Alternate pin definitions on BT848A and Bt849A.
14
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
UltraLock
UltraLock
The Challenge The line length (the interval between the midpoints of the falling edges of succeeding horizontal sync pulses) of analog video sources is not constant. For a stable source such as studio quality source or test signal generators, this variation is very small: 2 ns. However, for an unstable source such as a VCR, laser disk player, or TV tuner, line length variation is as much as a few microseconds. Digital display systems require a fixed number of pixels per line despite these variations. The BT848 employs a technique known as UltraLock to implement locking to the horizontal sync and the subcarrier of the incoming analog video signal and generating the required number of pixels per line. UltraLock is based on sampling using a fixed-frequency, stable clock. Since the video line length will vary, the number of samples generated using a fixed-frequency sample clock will also vary from line to line. If the number of generated samples per line is always greater than the number of samples per line required by the particular video format, the number of acquired samples can be reduced to fit the required number of pixels per line. The BT848 requires an 8*Fsc (28.64 MHz for NTSC and 35.47 MHz for PAL) crystal or oscillator input signal source. The 8*Fsc clock signal, or CLKx2, is divided down to CLKx1 internally (14.32 MHz for NTSC and 17.73 MHz for PAL). CLKx2 and CLKx1 are internal signals and are not made available to the system. UltraLock operates at CLKx1 although the input waveform is sampled at CLKx2 then low pass filtered and decimated to CLKx1 sample rate. At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels for PAL/SECAM within a nominal line time interval (63.5 s for NTSC and 64 s for PAL/SECAM). For square pixel NTSC and PAL/SECAM formats, there should only be 780 and 944 pixels per video line, respectively. This is because the square pixel clock rates are slower than a 4*Fsc clock rate, i.e., 12.27 MHz for NTSC and 14.75 MHz for PAL. UltraLock accommodates line length variations from nominal in the incoming video by always acquiring more samples, at an effective 4*Fsc rate, than are required by the particular video format and outputting the correct number of pixels per line. UltraLock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform.
Operation Principles of UltraLock
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(R)
L848A_A
15
FUNCTIONAL DESCRIPTION
UltraLock
BT848/848A/849A
Single-Chip Video Capture for PCI
The example illustrated in Figure 4 shows three successive lines of video being decoded for square pixel NTSC output. The first line is shorter than the nominal NTSC line time interval of 63.5 s. On this first line, a line time of 63.2 s sampled at 4*Fsc (14.32 MHz) generates only 905 pixels. The second line matches the nominal line time of 63.5 s and provides the expected 910 pixels. Finally, the third line is too long at 63.8 s within which 913 pixels are generated. In all three cases, UltraLock outputs only 780 pixels.
Figure 4. UltraLock Behavior for NTSC Square Pixel Output
Analog Waveform Line Length Pixels Per Line Pixels Sent to the FIFO by UltraLock 63.2 s 63.5 s 63.8 s
905 pixels
910 pixels
913 pixels
780 pixels
780 pixels
780 pixels
UltraLock can be used to extract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length (910 for NTSC and 1,135 for PAL/SECAM) and the worst case line length variation from nominal in the active region is greater than or equal to the required number of output pixels per line, i.e., P Nom + P Var P Desired where: = Nominal number of pixels per line at 4*Fsc sample rate (910 for NTSC, 1,135 for PAL/SECAM) PVar = Variation of pixel count from nominal at 4*Fsc (can be a positive or negative number) PDesired = Desired number of output pixels per line PNom
It should be noted that, for stable inputs, UltraLock guarantees the time between the falling edges of HRESET only to within one pixel. UltraLock does, however, guarantee the number of active pixels in a line as long as the above relationship holds.
16
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Composite Video Input Formats
Composite Video Input Formats
BT848 supports several composite video input formats. Table 4 shows the different video formats and some of the countries in which each format is used.
Table 4. Video Input Formats Supported by the BT848 Format NTSC-M NTSC-Japan(1) PAL-B PAL-D PAL-G PAL-H PAL-I PAL-M PAL-N Combination PAL-N SECAM 525 525 625 625 625 625 625 525 625 625 625 Lines 60 60 50 50 50 50 50 60 50 50 50 Fields FSC 3.58 MHz 3.58 MHz 4.43 MHz 4.43 MHz 4.43 MHz 4.43 MHz 4.43 MHz 3.58 MHz 3.58 MHz 4.43 MHz 4.43 MHz
Notes:(1). NTSC-Japan has 0 IRE setup.
The video decoder must be programmed appropriately for each of the composite video input formats. Table 5 lists the register values that need to be programmed for each input format.
L848A_A
17
FUNCTIONAL DESCRIPTION
Composite Video Input Formats
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 5. Register Values for Video Input Formats Register IFORM (0x01) Bit XTSEL [4:3] FORMAT [2:0] Cropping: HDELAY, VDELAY, VACTIVE, CROP HSCALE (0x08, 0x09) ADELAY (0x18) BDELAY (0x19) [7:0] in all five registers 01 001 Set to desired cropping values in registers 0x02AC NTSC-M NTSC-Japan 01 010 Set to NTSC-M square pixel values PAL-B, D, G, H, I 10 011 Set to desired cropping values in registers 0x033C 01 100 PAL-M PAL-N 10 101 PAL-N SECAM Combination 01 111 10 110
Set to NTSC-M Set to PAL-B, D, G, H, I square pixel square pixel values values
[15:0]
0x02AC
0x02AC
0x033C
0x033C(1)
0x033C
[7:0] [7:0]
0x68 0x5D
0x68 0x5D
0x7F 0x72
0x68 0x5D
0x7F 0x72
0x7F 0x72
0x7F tbd
Notes: (1). The BT848A and Bt849A will not output square pixel resolution for PAL N-combination. A smaller number of pixels must be output.
18
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Y/C Separation and Chroma Demodulation
Y/C Separation and Chroma Demodulation
Y/C separation and chroma decoding are handled as shown in Figure 5. Bandpass and notch filters are implemented to separate the composite video stream. The filter responses are shown in Figure 6. The optional chroma comb filter is implemented in the vertical scaling block. See the Video Scaling, Cropping, and Temporal Decimation section in this chapter. Figure 7 schematically describes the filtering and scaling operations. In addition to the Y/C separation and chroma demodulation illustrated in Figure 5, the BT848 also supports chrominance comb filtering as an optional filtering stage after chroma demodulation. The chroma demodulation generates baseband I and Q (NTSC) or U and V (PAL/SECAM) color difference signals. For S-Video operation, the digitized luma data bypasses the Y/C separation block completely, and the digitized chrominance is passed directly to the chroma demodulator. For monochrome operation, the Y/C separation block is also bypassed, and the saturation registers (SAT_U and SAT_V) are set to zero.
Figure 5. Y/C Separation and Chroma Demodulation for Composite Video
Composite
Notch Filter
Y
U
Low Pass Filter
sin V
Band Pass Filter Low Pass Filter
cos
Brooktree
(R)
L848A_A
19
FUNCTIONAL DESCRIPTION
Y/C Separation and Chroma Demodulation
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 6. Y/C Separation Filter Responses
Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM
NTSC
PAL/SECAM
NTSC
PAL/SECAM
Figure 7. Filtering and Scaling Horizontal Scaler Luminance
= A + BZ -1 + CZ -2 + DZ -3 + EZ -4 + FZ -5
Vertical Scaler Luminance
= C + DZ -1
Chrominance
= G + HZ
-1
Chrominance
1 1 -1 = -- + -- Z -22
(Chroma Comb)
Vertical Filter Options 1 -1 Luminance = -- ( 1 + z ) 2 1 -1 -2 = -- ( 1 + 2Z + 1Z ) 4 1 -1 -2 -3 = -- ( 1 + 3Z + 3Z + 1Z ) 8 1 -1 -2 -3 -4 = ----- ( 1 + 4Z + 6Z + 4Z + Z ) 16
Y
Optional 3 MHz Horizontal Low Pass Filter
6 Tap, 32 Phase Interpolation and Horizontal Scaling
On-chip Memory
Luma Comb Vertical Scaling Vertical Filtering
Y
C
2 Tap, 32 Phase Interpolation and Horizontal Scaling
On-chip Memory
Chroma Comb and Vertical Scaling
C
Note: Z-1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. The coefficients are determined by UltraLock and the scaling algorithm
20
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
Video Scaling, Cropping, and Temporal Decimation
The BT848 provides three mechanisms to reduce the amount of video pixel data in its output stream; down-scaling, cropping, and temporal decimation. All three can be controlled independently. Horizontal and Vertical Scaling The BT848 provides independent and arbitrary horizontal and vertical down scaling. The maximum scaling ratio is 16:1 in both X and Y dimensions. The maximum vertical scaling ratio is reduced from 16:1 when using frames to 8:1 when using fields. The different methods utilized for scaling luminance and chrominance are described in the following sections. The first stage in horizontal luminance scaling is an optional pre-filter which provides the capability to reduce anti-aliasing artifacts. It is generally desirable to limit the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequency components may create image artifacts in the resized image. The optional low pass filters shown in Figure 8 reduce the horizontal high-frequency spectrum in the luminance signal. Figure 9 and Figure 10 show the combined results of the optional low-pass filters, the luma notch filter and the 2x oversampling filter. Figure 12 shows the combined responses of the luma notch filter and the 2x oversampling filter. The BT848 implements horizontal scaling through poly-phase interpolation. The BT848 uses 32 different phases to accurately interpolate the value of a pixel. This provides an effective pixel jitter of less than 6 ns. In simple pixel- and line-dropping algorithms, non-integer scaling ratios introduce a step function in the video signal that effectively introduces high-frequency spectral components. Poly-phase interpolation accurately interpolates to the correct pixel and line position providing more accurate information. This results in aesthetically pleasing video as well as higher compression ratios in bandwidth limited applications. For vertical scaling, the BT848 uses a line store to implement four different filtering options. The filter characteristics are shown in Figure 11. The BT848 provides up to 5-tap filtering to ensure removal of aliasing artifacts. The number of taps in the vertical filter is set by the VTC register. The user may select 2, 3, 4 or 5 taps. The number of taps must be chosen in conjunction with the horizontal scale factor in order to ensure the needed data can fit in the internal FIFO (see the VFILT bits in the VTC register for limitations). As the scaling ratio is increased, the number of taps available for vertical scaling is increased. In addition to low-pass filtering, vertical interpolation is also employed to minimize artifacts when scaling to non-integer scaling ratios.
Luminance Scaling
Brooktree
(R)
L848A_A
21
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 8. Optional Horizontal Luma Low-Pass Filter Responses
NTSC QCIF QCIF CIF ICON ICON CIF
PAL/SECAM
Figure 9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC)
Pass Band CIF ICON CIF ICON QCIF
QCIF
Full Spectrum
Figure 10. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM)
Full Spectrum Pass Band CIF
CIF QCIF
ICON ICON
QCIF
22
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
Figure 11. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters
2-tap
3-tap
4-tap
5-tap
Figure 12. Combined Luma Notch and 2x Oversampling Filter Response
PAL/SECAM
NTSC
Brooktree
(R)
L848A_A
23
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Peaking (BT848A and Bt849A Only)
The BT848A enables four different peaking levels by programming the PEAK bit and HFILT bits in the SCLOOP register. The filters are shown in Figures 13 and 14.
Figure 13. Peaking Filters (BT848A/849A only)
HFILT = 00 HFILT = 01
HFILT = 10 HFILT = 11
Enhanced Resolution of Passband
HFILT = 00 HFILT = 01
HFILT = 10 HFILT = 11
24
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
Figure 14. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch (BT848A/849A only)
HFILT = 00 HFILT = 10 HFILT = 11 HFILT = 01
Enhanced Resolution of Passband HFILT = 00 HFILT = 01
HFILT = 10 HFILT = 11
Brooktree
(R)
L848A_A
25
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Chrominance Scaling
A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance. Vertical scaling of chrominance is implemented through chrominance comb filtering using a line store, followed by simple decimation or line dropping. The Horizontal Scaling Ratio Register (HSCALE) is programmed with the horizontal scaling ratio. When outputting unscaled video (in NTSC), the BT848 will produce 910 pixels per line. This corresponds to the pixel rate at fCLKx1 (4*Fsc). This register is the control for scaling the video to the desired size. For example, square pixel NTSC requires 780 samples per line, while CCIR601 requires 858 samples per line. HSCALE_HI and HSCALE_LO are two 8-bit registers that, when concatenated, form the 16-bit HSCALE register. The method below uses pixel ratios to determine the scaling ratio. The following formula should be used to determine the scaling ratio to be entered into the 16-bit register: NTSC: HSCALE = [ ( 910/Pdesired) - 1] * 4096 PAL/SECAM: HSCALE = [ ( 1135/Pdesired) - 1] * 4096 where: Pdesired = Desired number of pixels per line of video, including active, sync and blanking.
Scaling Registers
For example, to scale PAL/SECAM input to square pixel QCIF, the total number of horizontal pixels desired is 236: HSCALE = [ ( 1135/236 ) - 1 ] * 4096 = 12331 = 0x3CF2 An alternative method for determining the HSCALE value uses the ratio of the scaled active region to the unscaled active region as shown below: NTSC: PAL/SECAM: where: HSCALE = [ (754 / HACTIVE) - 1] * 4096 HSCALE = [ (922 / HACTIVE) - 1] * 4096
HACTIVE = Desired number of pixels per line of video, not including sync or blanking.
In this equation, the HACTIVE value cannot be cropped; it represents the total active region of the video line. This equation produces roughly the same result as using the full line length ratio shown in the first example. However, due to truncation, the HSCALE values determined using the active pixel ratio method will be slightly different than those obtained using the total line length pixel ratio method. The values in Table 6 were calculated using the full line length ratio.
26
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
The Vertical Scaling Ratio Register (VSCALE) is programmed with the vertical scaling ratio. It defines the number of vertical lines output by the BT848. The following formula should be used to determine the value to be entered into this 13-bit register. The loaded value is a two's-complement, negative value. VSCALE = ( 0x10000 - { [ ( scaling_ratio ) - 1] * 512 } ) & 0x1FFF For example, to scale PAL/SECAM input to square pixel QCIF, the total number of vertical lines is 156: VSCALE = ( 0x10000 - { [ ( 4/1 ) -1 ] * 512 } ) & 0x1FFF = 0x1A00 Note that only the 13 least significant bits of the VSCALE value are used; the five LSBs of VSCALE_HI and the 8-bit VSCALE_LO register form the 13-bit VSCALE register. The three MSBs of VSCALE_HI are used to control other functions. The user must take care not to alter the values of the three most significant bits when writing a vertical scaling value. The following C-code fragment illustrates changing the vertical scaling value:
#define #define #define #define BYTE unsigned char WORD unsigned int VSCALE_HI 0x13 VSCALE_LO 0x14
BYTE ReadFromBT848( BYTE regAddress ); void WriteToBT848( BYTE regAddress, BYTE regValue ); void SetBT848VScaling( WORD VSCALE ) { BYTE oldVscaleMSByte, newVscaleMSByte; /* get existing VscaleMSByte value from */ /* BT848 VSCALE_HI register */ oldVscaleMSByte = ReadFromBT848( VSCALE_HI ); /* create a new VscaleMSByte, preserving top 3 bits */ newVscaleMSByte = (oldVscaleMSByte & 0xE0) | (VSCALE >> 8); /* send the new VscaleMSByte to the VSCALE_HI reg */ WriteToBT848( VSCALE_HI, newVscaleMSByte ); /* send the new VscaleLSByte to the VSCALE_LO reg */ WriteToBT848( VSCALE_LO, (BYTE) VSCALE ); }
where: &
= bitwise AND | = bitwise OR >> = bit shift, MSB to LSB
If your target machine has sufficient memory to statically store the scaling values locally, the READ operation can be eliminated.
Brooktree
(R)
L848A_A
27
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Note on vertical scaling: When scaling below CIF resolution, it may be useful to use a single field as opposed to using both fields. Using a single field will ensure there are no inter-field motion artifacts on the scaled output. When performing single field scaling, the vertical scaling ratio will be twice as large as when scaling with both fields. For example, CIF scaling from one field does not require any vertical scaling, but when scaling from both fields, the scaling ratio is 50%. Also, the non-interlaced bit should be reset when scaling from a single field (INT=0 in the VSCALE_HI register). Table 6 lists scaling ratios for various video formats, and the register values required.
Table 6. Scaling Ratios for Popular Formats Using Frequency Values Total Resolution (including sync and blanking interval) 780x525 858x525 864x625 944x625 390x262 429x262 432x312 472x312 195x131 214x131 216x156 236x156 97x65 107x65 108x78 118x78 VSCALE Register Values Output Resolution (Active Pixels) HSCALE Register Values
Scaling Ratio
Format
Use Both Fields
Single Field
Full Resolution 1:1
NTSC SQ Pixel NTSC CCIR601 PAL CCIR601 PAL SQ Pixel NTSC SQ Pixel NTSC CCIR601 PAL CCIR601 PAL SQ Pixel NTSC SQ Pixel NTSC CCIR601 PAL CCIR601 PAL SQ Pixel NTSC SQ Pixel NTSC CCIR601 PAL CCIR601 PAL SQ Pixel
640x480 720x480 720x576 768x576 320x240 360x240 360x288 384x288 160x120 180x120 180x144 192x144 80x60 90x60 90x72 96x72
0x02AA 0x00F8 0x0504 0x033C 0x1555 0x11F0 0x1A09 0x1679 0x3AAA 0x3409 0x4412 0x3CF2 0x861A 0x7813 0x9825 0x89E5
0x0000 0x0000 0x0000 0x0000 0x1E00 0x1E00 0x1E00 0x1E00 0x1A00 0x1A00 0x1A00 0x1A00 0x1200 0x1200 0x1200 0x1200
N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x1E00 0x1E00 0x1E00 0x1E00 0x1A00 0x1A00 0x1A00 0x1A00
CIF 2:1
QCIF 4:1
ICON 8:1
Image Cropping
Cropping enables the user to output any subsection of the video image. The ACTIVE flag can be programmed to start and stop at any position on the video frame as shown in Figure 15. The start of the active area in the vertical direction is referenced to VRESET (beginning of a new field). In the horizontal direction it is referenced to HRESET (beginning of a new line). The dimensions of the active video region are defined by HDELAY, HACTIVE, VDELAY, and VACTIVE. All four registers are 10-bit values. The two MSBs of each register are contained in the CROP register, while the lower eight bits are in the respective HDELAY_LO, HACTIVE_LO, VDELAY_LO and VACTIVE_LO registers. The vertical and horizontal delay values determine the position of the cropped image within a frame while the horizontal and vertical active values set the pixel dimensions of the cropped image as illustrated in Figure 15.
28
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
Figure 15. Effect of the Cropping and Active Registers
Vertically Inactive Vertically Active HRESET Vertically Inactive Vertically Active
(R)
Video frame
Brooktree
Beginning of a New Frame VRESET
Cropped image
Horizontally Inactive
Horizontally Active
Video frame
Cropped image scaled to 1/2 size
Horizontally Inactive
Horizontally Active
Beginning of a New Line
L848A_A
29
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Cropping Registers
The Horizontal Delay Register (HDELAY) is programmed with the delay between the falling edge of HRESET and the rising edge of ACTIVE. The count is programmed with respect to the scaled frequency clock. Note that HDELAY should always be an even number. The Horizontal Active Register (HACTIVE) is programmed with the actual number of active pixels per line of video. This is equivalent to the number of scaled pixels that the BT848 should output on a line. For example, if this register contained 90, and HSCALE was programmed to downscale by 4:1, then 90 active pixels would be output. The 90 pixels would be a 4:1 scaled image of the 360 pixels (at CLKx1) starting at count HDELAY. HACTIVE is restricted in the following manner: HACTIVE + HDELAY Total Number of Scaled Pixels. For example, in the NTSC square pixel format, there is a total of 780 pixels, including blanking, sync and active regions. Therefore: HACTIVE + HDELAY 780. When scaled by 2:1 for CIF, the total number of active pixels is 390. Therefore: HACTIVE +HDELAY 390. The HDELAY register is programmed with the number of scaled pixels between HRESET and the first active pixel. Because the front porch is defined as the distance between the last active pixel and the next horizontal sync, the video line can be considered in three components: HDELAY, HACTIVE and the front porch. See Figure 16. When cropping is not implemented, the number of clocks at the 4x sample rate (the CLKx1 rate) in each of these regions is shown below:
CLKx1 Front Porch NTSC PAL/SECAM 21 27
CLKx1 HDELAY 135 186
CLKx1 HACTIVE 754 922
CLKx1 Total 910 1135
The value for HDELAY is calculated using the following formula: HDELAY = [(CLKx1_HDELAY / CLKx1_HACTIVE) * HACTIVE] & 0x3FE CLKx1_HDELAY and CLKx1_HACTIVE are constant values, so the equation becomes: NTSC:HDELAY = [(135 / 754) * HACTIVE] & 0x3FE PAL/SECAM:HDELAY = [(186 / 922) * HACTIVE] & 0x3FE In this equation, the HACTIVE value cannot be cropped.
30
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
Figure 16. Regions of the Video Signal
HDELAY
Front Porch
HACTIVE
The Vertical Delay Register (VDELAY) is programmed with the delay between the rising edge of VRESET and the start of active video lines. It determines how many lines to skip before initiating the ACTIVE signal. It is programmed with the number of lines to skip at the beginning of a frame. The Vertical Active Register (VACTIVE) is programmed with the number of lines used in the vertical scaling process. The actual number of vertical lines output from the BT848 is equal to this register times the vertical scaling ratio. If VSCALE is set to 0x1A00 (4:1) then the actual number of lines output is VACTIVE/4. If VSCALE is set to 0x0000 (1:1) then VACTIVE contains the actual number of vertical lines output. Note: It is important to note the difference between the implementation of the horizontal registers (HSCALE, HDELAY, and HACTIVE) and the vertical registers (VSCALE, VDELAY, and VACTIVE). Horizontally, HDELAY and HACTIVE are programmed with respect to the scaled pixels defined by HSCALE. Vertically, VDELAY and VACTIVE are programmed with respect to the number of lines before scaling (before VSCALE is applied). Temporal Decimation Temporal decimation provides a solution for video synchronization during periods when full frame rate can not be supported due to bandwidth and system restrictions. For example, when capturing live video for storage, system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate. If these restrictions limit the frame rate to 15 frames per second, the BT848's time scaling operation will enable the system to capture every other frame instead of allowing the hard disk timing restrictions to dictate which frame to capture. This maintains an even distribution of captured frames and alleviates the "jerky" effects caused by systems that simply burst in data when the bandwidth becomes available. The BT848 provides temporal decimation on either a field or frame basis. The temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC) or 1 to 50 (PAL/SECAM). This value is the number of fields or frames skipped by the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM. Skipped fields and frames are considered inactive, which is indicated by the ACTIVE pin remaining low.
Brooktree
(R)
L848A_A
31
FUNCTIONAL DESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
BT848/848A/849A
Single-Chip Video Capture for PCI
Examples: TDEC = 0x02 Decimation is performed by frames. Two frames are skipped per 60 frames of video, assuming NTSC decoding. Frames 1-29 are output normally, then ACTIVE remains low for one frame. Frames 31-59 are then output followed by another frame of inactive video. Decimation is performed by fields. Thirty fields are output per 60 fields of video, assuming NTSC decoding. This value outputs every other field (every odd field) of video starting with field one in frame one. Decimation is performed by frames. One frame is skipped per 50 frames of video, assuming PAL/SECAM decoding. Decimation is not performed. Full frame rate video is output by the BT848.
TDEC = 0x9E
TDEC = 0x01
TDEC = 0x00
When changing the programming in the temporal decimation register, 0x00 should be loaded first, and then the decimation value. This will ensure that the decimation counter is reset to zero. If zero is not first loaded, the decimation may start on any field or frame in the sequence of 60 (or 50 for PAL/SECAM). On power-up, this preload is not necessary because the counter is internally reset. When decimating fields, the FLDALIGN bit in the TDEC register can be programmed to choose whether the decimation starts with an odd field or an even field. If the FLDALIGN bit is set to logical zero, the first field that is dropped during the decimation process will be an odd field. Conversely, setting the FLDALIGN bit to logical one causes the even field to be dropped first in the decimation process.
32
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Adjustments
Video Adjustments
The BT848 provides programmable hue, contrast, saturation, and brightness. The Hue Adjust Register (HUE) The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC, the hue of the video signal is defined as the phase of the subcarrier with reference to the burst. The value programmed in this register is added to or subtracted from the phase of the subcarrier, which effectively changes the hue of the video. The hue can be shifted by plus or minus 90 degrees. Because of the nature of PAL/SECAM encoding, hue adjustments can not be made when decoding PAL/SECAM. The Contrast Adjust Register (also called the luma gain) provides the ability to change the contrast from approximately 0% to 200% of the original value. The decoded luma value is multiplied by the 9-bit coefficient loaded into this register. The Saturation Adjust Registers are additional color adjustment registers. It is a multiplicative gain of the U and V signals. The value programmed in these registers are the coefficients for the multiplication. The saturation range is from approximately 0% to 200% of the original value. The Brightness Register is simply an offset for the decoded luma value. The programmed value is added to or subtracted from the original luma value which changes the brightness of the video output. The luma output is in the range of 0 to 255. Brightness adjustment can be made over a range of -128 to +127.
The Contrast Adjust Register (CONTRAST)
The Saturation Adjust Registers (SAT_U, SAT_V)
The Brightness Register (BRIGHT)
Automatic Chrominance Gain Control
The Automatic Chrominance Gain Control compensates for reduced chrominance and color-burst amplitudes. Here, the color-burst amplitude is calculated and compared to nominal. The color-difference signals are then increased or decreased in amplitude according to the color-burst amplitude difference from nominal. The range of chrominance gain is 0.5-2 times the original amplitude. This compensation coefficient is then multiplied by the Saturation Adjust value for a total chrominance gain range of 0-2 times the original signal. Automatic chrominance gain control may be disabled.
Brooktree
(R)
L848A_A
33
FUNCTIONAL DESCRIPTION
Low Color Detection and Removal
BT848/848A/849A
Single-Chip Video Capture for PCI
Low Color Detection and Removal
If a color-burst of 25 percent (NTSC) or 35 percent (PAL/SECAM) or less of the nominal amplitude is detected for 127 consecutive scan lines, the color-difference signals U and V are set to zero. When the low color detection is active, the reduced chrominance signal is still separated from the composite signal to generate the luminance portion of the signal. The resulting Cr and Cb values are 128. Output of the chrominance signal is re-enabled when a color-burst of 43 percent (NTSC) or 60 percent (PAL/SECAM) or greater of nominal amplitude is detected for 127 consecutive scan lines. Low color detection and removal may be disabled.
Coring
The BT848 video decoder can perform a coring function, in which it forces all values below a programmed level to be zero. This is useful because the human eye is more sensitive to variations in black images. By taking near black images and turning them into black, the image appears clearer to the eye. Four coring values can be selected: 0, 8, 16, or 32 above black. If the total luminance level is below the selected limit, the luminance signal is truncated to the black value. If the luma range is limited (i.e. black is 16), then the coring circuitry automatically takes this into account and references the appropriate value for black. Coring is illustrated in Figure 17.
Figure 17. Coring Map
Output Luma Value
32 16 8 0 0 8 16 32
Calculated Luma Value
34
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
VBI Data Output Interface
VBI Data Output Interface
A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM. Figure 18 illustrates an NTSC video frame, in which there are a number of distinct regions. The video image or picture data is contained in the odd and even fields within lines 21 to 263 and lines 283 to 525 respectively. Each field of video also contains a region for vertical synchronization (lines 1 through 9 and 263 through 272) as well as a region which can contain non-video ancillary data (lines 10 through 20 and 272 through 283). We will refer to these regions which are between the vertical synchronization region and the video picture region as the Vertical Blanking Interval or VBI portion of the video signal.
Figure 18. Regions of the Video Frame
Lines 1-9 Lines 10-20 Vertical Synchronization Region Vertical Blanking Interval Odd Field Even Field
Lines 21-263
Video Image Region
Lines 263-272 Lines 272-283
Vertical Synchronization Region Vertical Blanking Interval
Lines 283-525
Video Image Region
The BT848 is able to capture VBI data and store it in the host memory for later processing by the BT848 VBI decoder software. Two modes of VBI capture exist: VBI line output mode and VBI frame output mode. Both types of data may be captured during the same field. In the VBI line output mode, VBI capture occurs during the vertical blanking interval. The start of VBI data capture is set by the VBI_HDELAY bit in the VBI Packet Size/Delay register, and is in reference to the trailing edge of the HRESET signal. The number of DWORDs of VBI data is selected by the user. Each DWORD contains 4 VBI bytes, and each VBI pixel consists of two VBI samples. For example, for a given 800 pixel line in the VBI region, there exist 1600 VBI samples, which is equivalent to 400 DWORDs of VBI data. The VBI_PKT_HI and VBI_PKT_LO register bits are concatenated to create the 9-bit value for the number of DWORDs to be captured.
Brooktree
(R)
L848A_A
35
FUNCTIONAL DESCRIPTION
VBI Data Output Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
VBI line data capture occurs when the CAPTURE_EVEN register bit is enabled for the even field and CAPTURE_ODD register bit is enabled for the odd field. The VBI data is sampled at a rate of 8*Fsc and is stored in the FIFO as a sequence of 8-bit samples. Line mode VBI data is horizontally bound beginning at VBI_HDELAY pixels from the trailing edge of HRESET and ending after the VBI_PKT number of DWORDs. Line mode VBI data is vertically bound starting at the first line following VRESET and ending at VACTIVE. VBI register settings can only be changed on a per frame basis. The VBI timing is illustrated in Figure 19.
Figure 19. VBI Timing
VRESET VBI_HDELAY VDELAY VBI Line Data Capture HRESET VACTIVE VBI_PKT #
Once the VBI data has been captured and stored in the BT848 FIFO, it is treated as any other type of data. It is output over the PCI bus via RISC instructions. If the number of VBI lines desired by the user is smaller than the entire vertical blanking region, the extra data will be discarded by the use of the SKIP RISC instruction. Alternatively, if the user desires a larger VBI region in the VBI line output mode, the vertical blanking region can be extended by setting the VDELAY register bit to the appropriate value. The VBI line output mode can in effect extend the VBI region to the entire field. Figure 20 shows a block diagram of the VBI section.
Figure 20. VBI Section Block Diagram
Video Data Format Converter YCrCb 4:2:2, 4:1:1 Analog Video ADC VBI Data CSC/Gamma 8-Bit Dither Format MUX FIFOs Y: 70x36 Cb: 35x36 Cr: 35x36 # DWORDS Instruction Queue DMA Controller PCI Initiator PCI Bus
Address Generator FIFO Data MUX
36
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
VBI Data Output Interface
In the VBI frame output mode, the VBI data capture occurs in the active video region and includes all the horizontal blank/sync information in the data stream. The data is vertically bound beginning at the first line during VACTIVE and ending after a fixed number of packets. The data stream is packetized into a series of 256-DWORD blocks. A fixed number of DWORD blocks (434 for NTSC and 650 for PAL) are captured during each field. This is equivalent to 111,104 DWORDs for NTSC (434 * 256 DWORDS) and 166,400 DWORDs for PAL (650 * 256 DWORDs) per field. The VBI frame capture region may be extended to include the 10 lines prior to the default VACTIVE region by setting the EXT_FRAME register bit. VDELAY must also be set to its minimum value of 2. The extended DWORD block size is 450 DWORD blocks for NTSC and 674 DWORD blocks for PAL. The VBI frame data capture occurs during the even field when the CAPTURE_EVEN register bit is set and the COLOR_EVEN bit is set to raw mode, and during the odd field when the CAPTURE_ODD register bit is set and the COLOR_ODD bit is set to raw mode. The captured data stream is continuous and not aligned with HSYNC.
Brooktree
(R)
L848A_A
37
FUNCTIONAL DESCRIPTION
Video Data Format Conversion
BT848/848A/849A
Single-Chip Video Capture for PCI
Video Data Format Conversion
Pixel Data Path The video decoder/scaler portion of the BT848 generates a video data stream in packed 4:2:2 YCrCb format. The video data is then color space converted and formatted in a 32-bit wide DWORD. Figure 21 shows the steps in converting the video data from packed 4:2:2 YCrCb to the desired format. The YCrCb 4:2:2 data is up-sampled to 4:4:4 format prior to conversion to RGB. It can then be dithered, have gamma correction removed, or be presented directly to the byte swap circuit. In the case where 4:1:1 data is desired, the 4:2:2 data is first down sampled, then packed into BtYUV format or converted to planar format and vertically subsampled to achieve the YUV9 format. Alternatively, packed 4:2:2 data may be converted to planar 4:2:2 and vertically sub-sampled to YUV12 format. The vertical subsampling is achieved via the appropriate DMA instructions (see the DMA controller section). BT848 also offers a Y8 color format, in which the chroma component of the packed 4:2:2 data is stripped and the luma component is packed into 8 bits. This format is otherwise known as gray scale. Table 7 shows the various color formats supported by the BT848 and the mapping of the bytes onto 32-bit DWORDs. In addition to the pixel information, the BT848's Video Data Format Converter provides four bits of video control status code to the FIFO. These four bits of status code STATUS[3:0] are based on inputs from the video decoder/scaler block of the BT848, and convey information about the pixel data and the state of the video timing (Figure 21). STATUS[3:0] are used to specify the FIFO mode (packed or planar), provide information regarding the pixel data (respective position of the pixel and number of valid bytes), to indicate if the pixel data is valid, and to signal the end of a capture enabled field. See Table 9 in the FIFO section for a full list of the status codes and descriptions.
Video Control Code Status Data
38
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Data Format Conversion
Figure 21. Video Data Format Converter
RGB Gamma Correction Removal From BT848 Color Video Decoder/Scaler Up-sample 4:4:4 Space Chroma Packed 4:2:2 Conversion Packed 4:2:2 Strip Chroma and Pack Luma Sub-sample Chroma Dither Linear RGB FI[31:0] 8-bit Dithered RGB Byte Swap Y8 (Gray Scale) Planar 4:2:2 Planar 4:1:1 BtYUV DMA Controller Vertical Sub-sample Chroma From FIFO To FIFO
Packed 4:2:2
Packed 4:1:1
Packed to Planar Conversion Packed to Planar Conversion Internal Control Signals from BT848 Video Decoder Status[3:0]
Planar 4:1:1
Planar 4:2:2 FI[35:32] To FIFO
Video FIFO Write Signals Control Code Generator FIFO Write Clock
Planar YUV12
Planar YUV9
Brooktree
(R)
L848A_A
39
FUNCTIONAL DESCRIPTION
Video Data Format Conversion
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 7. Color Formats Pixel Data [31:0] Format DWORD Byte Lane 3 [31:24] Alpha B1 G2 R3 Byte Lane 2 [23:16] R R0 B2 G3 Byte Lane 1 [15:8] G G0 R1 B3 Byte Lane 0 [7:0] B B0 G1 R2
RGB32(1)
dw0 dw0
RGB24
dw1 dw2
RGB16 RGB15 YUY2--YCrCb 4:2:2(2)
dw0 dw0 dw0 dw1 dw0
{R1[7:3],G1[7:2],B1[7:3]} {0,R1[7:3],G1[7:3],B1[7:3]} Cr0 Cr2 Y1 Y3 Y7 Y3 B3 D3 Y3 Y7 Cb6 Cr6 Y1 Y3 Cr0 Cr4 Y6 Y2 B2 D2 Y2 Y6 Cb4 Cr4
{R0[7:3],G0[7:2],B0[7:3]} {0,R0[7:3],G0[7:3],B0[7:3]} Cb0 Cb2 Y0 Y2 Y5 Y1 B1 D1 Y1 Y5 Cb2 Cr2 Y0 Y2 Cb0 Cb4 Y4 Y0 B0 D0 Y0 Y4 Cb0 Cr0
BtYUV--YCrCb 4:1:1
dw1 dw2
Y8 (Gray Scale) 8-bit Dithered VBI Data
dw0 dw0 dw0 dw0 FIFO1 dw1 FIFO1
YCrCb 4:2:2 Planar dw0 FIFO2 dw0 FIFO3 YUV12 Planar
Vertically sub-sampled to 4:2:2 by the DMA controller dw0 FIFO1 dw1 FIFO1 dw2 FIFO1 Y3 Y7 Y11 Y15 Cb12 Cr12 Y2 Y6 Y10 Y14 Cb8 Cr8 Y1 Y5 Y9 Y13 Cb4 Cr4 Y0 Y4 Y8 Y12 Cb0 Cr0
YCrCb 4:1:1 Planar dw3 FIFO1 dw0 FIFO2 dw0 FIFO3 YUV9 Planar
Vertically sub-sampled to 4:1:1 by the DMA controller
Notes: (1). The alpha byte can be written as 0 data, or not written. (2). UYVY can be achieved by byte swapping.
40
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video Data Format Conversion
YCrCb to RGB Conversion
The 4:2:2 YCrCb data stream from the video decoder portion of the BT848 must be converted to 4:4:4 YCrCb before the RGB conversion occurs, using an interpolation filter on the chroma data path. The even valid chroma data pass through unmodified, while the odd data is generated by averaging adjacent even data. The chroma component is upsampled using the following equations: For n = 0, 2, 4, etc. Cbn = Cbn Crn = Crn Cbn+1 = (Cbn + Cbn+2)/2 Crn+1 = (Crn + Crn+2)/2 RGB Conversion: R = 1.164(Y-16) + 1.596(Cr-128) G = 1.164(Y-16) - 0.813(Cr-128) - 0.391(Cb-128) B = 1.164(Y-16) + 2.018(Cb-128) Y range = [16,235] Cr/Cb range = [16,240] RGB range = [0,255]
Gamma Correction Removal
BT848 provides gamma correction removal capability. The available gamma values are: NTSC: RGBout = RGBin2.2 PAL: RGBout = RGBin2.8 Gamma correction removal capability is not programmable on a field basis. Furthermore, gamma correction removal is not available when YCrCb data is output.
YCrCb Sub-sampling
The 4:2:2 data stream is horizontally sub-sampled to 4:1:1 using the following equations: For n = 0, 4, 8, etc.: Cbn = (Cbn + Cbn+2) Crn = (Crn + Crn+2) Vertical sub-sampling is supported by BT848's YUV9 and YUV12 planar modes. In these modes, the video data is first planarized and placed in the FIFO as 4:2:2 planar or 4:1:1 planar data. The FIFO data is then vertically sub-sampled to 4:1:1 for YUV9 and 4:2:2 for YUV12 formats. The vertical sub-sampling is performed via RISC instructions that are executed by the DMA controller. Table 7 shows an example of a 4 pixel line for YUV9 and YUV12 formats. In the YUV12 format. Line 2 of Cr/Cb data is discarded and hence 4:2:2 vertical sub-sampling is achieved. In the YUV9 format, lines 2-4 of Cr/Cb data are discarded and hence 4:1:1 vertical sub-sampling is achieved.
Brooktree
(R)
L848A_A
41
FUNCTIONAL DESCRIPTION
Video Data Format Conversion
BT848/848A/849A
Single-Chip Video Capture for PCI
Byte Swapping
Before the data enters the FIFO it passes through a 4-way mux to allow swapping of the bytes to support Macintosh (big endian) color data formats. The pixel DWORD PD[31:0] maps onto the FIFO input FI[31:0]. The byte-swap mux remaps the data bytes, but byte lane 0 or bits[7:0] will still be considered the first byte of the scan line.
Table 8. Byte Swapping Map Word Swap Byte Swap FIFO Inputs [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] 0 0 1 0 1 1
Outputs of FIFO Data Formatter [23:16] [31:24] [7:0] [15:8] [15:8] [7:0] [31:24] [23:16] [7:0] [15:8] [23:16] [31:24]
Note: The byte swapping mode is disabled during VBI data.
42
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video and Control Data FIFO
Video and Control Data FIFO
The FIFO block accepts data from the video data format conversion process, buffers the data in FIFO memory, then outputs DWORDs to the DMA Controller to be burst onto the PCI bus. Logical Organization The 630-byte data FIFO is logically organized into 3 segments: FIFO1 = 70 words deep by 36 bits wide, FIFO2 = 35 x 36 bits, and FIFO3 = 35 x 36 bits. Each of the 140 FIFO data words provide for one DWORD of pixel data and four bits of video control code status. This is illustrated in Figure 22. The FIFOs are large enough to support efficient size burst transfers (16 to 32 data phases) in planar as well as packed mode.
Figure 22. Data FIFO Block Diagram
From FIFO Input Data Formatter FI[35:32] FI[31:0] Control Status Code FIFO Write Signals 3 (From VDFC) Pixel Data
FIFO1 70x36
Y Cb
3
FIFO Read Signals (From DMA Controller)
FIFO Enable Signal (From Control Register) FIFO Write Clock (Synchronous to Video Decoder Pixel Clock)
FIFO2 35x36 FIFO3 35x36
FIFO Read Clock (Synchronous to PCI Clock)
Cr
FIFO1 Output
FIFO2 FIFO3 Output Output
Brooktree
(R)
L848A_A
43
FUNCTIONAL DESCRIPTION
Video and Control Data FIFO
BT848/848A/849A
Single-Chip Video Capture for PCI
FIFO Data Interface
Loading data into the FIFO can begin only when valid pixels are present during the even or the odd field. The pixel DWORD PD[31:0] is stored in FI[31:0], and the video control code STATUS[3:0] is stored in FI[35:32]. The VBI data will be included in the captured sequence if VBI capture capability is enabled. The four bits of STATUS are used to encode information about the pixel data and the state of the video timing unit (see Table 9). Video timing and control information are passed through the FIFO along with the data stream. The FIFO buffer isolates the asynchronous video input and PCI output domains. Control of the input stream can only occur from the video timing unit of the video decoder and from the configured registers. The interaction and synchronization of the DMA Controller and the RISC instruction sequence will rely solely on the output side of the FIFO.
Table 9. Status Bits Status[3:0] 0110 1110 0010 0001 1101 1001 0101 0100 1100 0000 FM1 FM3 SOL EOL EOL EOL EOL VRE VRO PXV Description FIFO Mode: packed data to follow FIFO Mode: planar data to follow First active pixel/data DWORD of scan line Last active pixel/data DWORD of scan line, 4 Valid Bytes Last active pixel/data DWORD of scan line, 3 Valid Bytes Last active pixel/data DWORD of scan line, 2 Valid Bytes Last active pixel/data DWORD of scan line, 1 Valid Byte VRESET following an even field-falling edge of FIELD VRESET following an odd field-rising edge of FIELD Valid pixel/data DWORD
Capturing data to the FIFO always begins with a FIFO mode indicator code followed by pixel data. The FIFO Mode Indicator is to be stored in the FIFOs at the beginning of every capture-enabled field, when the data format is changed mid-field such as transitioning from packed VBI data to planar mode, and when video capture of a field is asynchronously enabled. The mode status codes are always stored in planar format. FIFO1 receives two copies of the status code, while FIFO2 and FIFO3 each receive one copy. The SOL code is packed in the FIFO with the first valid pixel data byte, which is the first pixel DWORD for the scan line. The EOL code is packed in the FIFO with the last valid pixel data byte, which is the last DWORD location written to the FIFO for the scan line. The EOL code indicates one to four valid bytes. The VRE/VRO code is stored in the FIFO at the end of a capture-enabled field. The DMA controller activates the appropriate PCI byte enables by the time a given DWORD arrives on the output side of the FIFO.
44
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Video and Control Data FIFO
The DMA Controller will guarantee that the FIFO does not fill, therefore the VDFC has no responsibility for FIFO overruns. The DMA Controller will be able to resynchronize to data streams that are shorter or longer than expected. Note that planar mode and packed mode data can be present in the FIFOs at the same time if a bus access latency persists across a FIELD transition, or if packed VBI data proceeds planar YCrCb data. Physical Implementation The three FIFO outputs are delivered in parallel so that the DMA Controller can monitor the FIFOs and perform skipping (reading and discarding data), if necessary, on all three simultaneously. Due to the latency in determining the number of DWORDs placed in each FIFO, a FIFO Full (FFULL) condition is indicated prior to the FIFO count reaching the maximum FIFO size. The FIFO is considered FFULL when the FIFO Count (FCNT) value equals or exceeds the FFULL value. FSIZE1 = 70 FFULL1 = 68 FSIZE2 = 35 FFULL2 = 34 FSIZE3 = 35 FFULL3 = 34 FSIZET = 140 FFULLT = 136 A read must occur on the same cycle as FFULL, otherwise data will overflow and will be overwritten. The maximum bus latencies for various video formats and modes are shown in Table 10. FIFO Input/Output Rates The input and output ports of the BT848's FIFO can operate simultaneously and are asynchronous to one another. The maximum FIFO input rate would be for consecutive writes of PAL video at 17.73 MHz. However, there will never be consecutive-pixel-cycle writes to the same FIFO. The fastest FIFO write sequence is F1, F2, F1, F3. Therefore, the fastest write rate to any FIFO is less than or equal to half of the pixel rate. The maximum FIFO output read rate is one FIFO word at the PCI clock rate (33 MHz). All three FIFOs can be read simultaneously. Some bus systems may be designed with PCI clocks slower than 33 MHz. The BT848 data FIFO only supports systems where the maximum input data rate is less than the output data rate. It can support a input video clock (17.73 MHz) faster than the PCI clock (16 MHz) as long as the video data rate does not exceed the available PCI burst rate.
Brooktree
(R)
L848A_A
45
FUNCTIONAL DESCRIPTION
Video and Control Data FIFO
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 10. Table of PCI Bus Access Latencies Max Bus Latency Before FIFO Overflow (uS) 10 13 20 27 41 20 27 41 55 83 8 11 17 23 34 17 23 34 46 69
Video Format
Resolution
Mode
NTSC 30 fps
640 x 480
RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 Y8, 8-bit dithered, VBI
NTSC 30 fps
320 x 240
RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 Y8, 8-bit dithered, VBI
PAL/SECAM 25 fps
768 x 576
RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 Y8, 8-bit dithered, VBI
PAL/SECAM 25 fps
384 x 288
RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 Y8, 8-bit dithered, VBI
Effective Rate:NTSC (Pixels/Sec) NTSC NTSC PAL PAL
640 x 480 320 x 240 720 x 480 768 x 576 384 x 288
12.27 6.14 13.50 14.75 7.38
The above figures are based on a 33.33 MHz PCI bus. Max Bus Latency before FIFO Overflow (uS) = FIFO FAFULL Limit (Effective Rate*Number of Bytes/Pixel)
46
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
DMA Controller
The BT848 incorporates a unique DMA controller architecture which gives the capture system great flexibility in its ability to deliver data to memory. It is architected as a small RISC engine which runs on a set of instructions generated and maintained in host system memory by the BT848 device driver software. In this architecture, the DMA can dynamically change target memory address from one video line to the next. This enables multiple memory targets to be established for various components of each video frame. For example, an NTSC video frame contains four discrete components which require separate target memory locations: even field video image data, odd field video image data, line 21 closed captioning data and line 15 teletext data. The BT848 DMA can concurrently support a display memory target for the even field image, and three separate system memory targets for the odd field image, line 21 data and line 15 data respectively. The BT848 device driver software creates a RISC program which runs the DMA controller. The RISC program resides in host system memory. Through the use of the PCI target, the RISC program puts its own starting address in a BT848 register and makes it available to the DMA controller. The DMA controller then requests that the PCI initiator fetch an instruction. The RISC instructions available are WRITE, SKIP, SYNC, and JUMP. The decoded composite video data is stored in the BT848 FIFOs and the DMA controller presents the data to the PCI initiator and requests that the data be output to the target memory. The PCI initiator outputs the pixel data on the PCI bus after gaining access to the PCI bus. It is the responsibility of the DMA controller to prevent and manage the overflow of the BT848 FIFOs. This is illustrated in Figure 23.
Brooktree
(R)
L848A_A
47
FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 23. RISC Block Diagram
Control Signals DMA Controller Address/Data Decoder FIFO Read Signals FIFO Status Bits Number of From FIFO
Bytes
PCI Initiator RISC Instructions
To PCI Bus Interface
Op Code RISC Decoder
RISC Instruction Buffer DMA Address and Byte Counter FIFO Data Buffer Pixel Data [31:0] Address
Available
in FIFO
FIFO Output [31:0]
RISC Program Start Address
RISC Program Counter
Target Memory
The BT848's FIFO DWORDs are perfectly aligned to the PCI bus, i.e. bit 0 of the FIFO DWORDs lines up with bit AD[0] on the PCI bus. Thus, video scan line data is aligned to target memory locations, and data path combinational logic between the FIFO and the PCI bus is not required. The target memory for a given scan line of data is assumed to be linear, incrementing, and contiguous. For a 1024-pixel scan line a maximum of 4 KB of contiguous physical memory is required. Each scan line can be stored anywhere in the 32-bit address space. A scan line can be broken into segments with each segment sent to a different target area. An image buffer can be allocated to line fragments anywhere in the physical memory, as the line sequence is arbitrary.
48
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
RISC Program Setup and Synchronization
There are two independent sets of RISC instructions in the host memory, one for the odd field and the other for the even field. The first field begins with a synchronization instruction (See SYNC in Table 11) indicating packed or planar data from the FIFO (STATUS[3:0] = FM1 or FM3), and it ends with a SYNC instruction indicating an even or an odd field to follow (STATUS[3:0] = VRE or VRO). The second field begins with a SYNC instruction and ends with a SYNC instruction followed by a JUMP instruction back to the first field. The SYNC instructions allow the synchronization of the FIFO output and the RISC program start/end points. The software will set up a pixel data flow by creating a RISC instruction sequence in the host memory for the odd and even fields. The DMA controller normally branches through the RISC instruction sequence via JUMP instructions. The RISC program sequence only needs to be changed when the parameters of the video capture/preview mode change, otherwise the DMA controller continuously cycles through the same program which is set up once for control of an entire frame. There exist five types of packed mode RISC instructions (WRITE, WRITEC, SKIP, SYNC, JUMP) to control the data stored in the FIFO. Three additional planar mode instructions exist, which replace the simple packed mode WRITE/SKIP instructions. Instruction details are listed in Table 11. The DMA controller switches from packed mode to planar mode or vice versa based on the status codes flowing through the FIFOs along with the pixel data.
RISC Instructions
Brooktree
(R)
L848A_A
49
FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 11. RISC Instructions (1 of 4) Instruction WRITE Opcode 0001 DWORDs 2 Description Write packed mode pixels to memory from the FIFO beginning at the specified target address. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [31:0] WRITE123 1001 5 32-bit Target Address Byte Address of first pixel byte. Byte Count Byte Enables Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode
Write pixels to memory in planar mode from the FIFOs beginning at the specified target addresses. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] DWORD2: [31:0] DWORD3: [31:0] DWORD4: [31:0] 32-bit Target Address Byte Address for Cr data from FIFO3 32-bit Target Address Byte Address for Cb data from FIFO2 32-bit Target Address Byte Address for Y data from FIFO1 Byte Count #2 Byte count #3 Byte transfer count from FIFO2 Byte transfer count from FIFO3 Byte Count #1 Byte Enables Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode Byte transfer count from FIFO1
50
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
Table 11. RISC Instructions (2 of 4) Instruction WRITE1S23 Opcode 1011 DWORDs 3 Description Write pixels to memory in planar mode from the FIFO1 beginning at the specified target addresses. Skip pixels from FIFO2 and FIFO3. This instruction is used to achieve the YUV9 and YUV12 color modes, where the chroma components are sub-sampled. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] DWORD2: [31:0] WRITEC 0101 1 32-bit Target Address Byte Address for Y data from FIFO1 Byte Count #2 Byte count #3 Byte skip count from FIFO2 Byte skip count from FIFO3 Byte Count #1 Byte Enables Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode Byte transfer count from FIFO1
Write packed mode pixels to memory from the FIFO continuing from the current target address. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] Byte Count Byte Enables Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode Cannot be set
Brooktree
(R)
L848A_A
51
FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 11. RISC Instructions (3 of 4) Instruction SKIP Opcode 0010 DWORDs 1 Description Skip pixels by discarding byte count # of bytes from the FIFO. This may start and stop in the middle of a DWORD. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] SKIP123 1010 2 Byte Count Reserved Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode
Skip pixels in planar mode by discarding byte count #1 of bytes from the FIFO1 and byte count #2 from FIFO2 and FIFO3. This may start and stop in the middle of a DWORD. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] Byte Count #2 Byte Count #3 Byte Count #1 Reserved Reset/Set RISC_STATUS IRQ Reserved EOL SOL Opcode
52
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
Table 11. RISC Instructions (4 of 4) Instruction JUMP Opcode 0111 DWORDs 2 Description Jump the RISC program counter to the jump address. This allows unconditional branching of the sequencer program. DWORD0: [15:0] [23:16] [24] [27:25] [31:28] DWORD1: [31:0] SYNC 1000 2 Jump Address DWORD-aligned Reserved Reset/Set RISC_STATUS IRQ Reserved Opcode
Skip all data in FIFO until the RISC instruction status bits equal to the FIFO status bits. DWORD0: [3:0] [14:4] [15] [23:16] [24] [27:25] [31:28] DWORD1: [31:0] Reserved Status Reserved RESYNC Reset/Set RISC_STATUS IRQ Reserved Opcode A value of 1 disables FDSR errors
Brooktree
(R)
L848A_A
53
FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
Each RISC instruction consists of 1 to 5 DWORDs. The 32 bits in the DWORDs relay information such as the opcode, target address, status codes, synchronization codes, byte count/enables, and start/end of line codes. The SOL bit in the WRITE and SKIP instructions indicate that this particular instruction is the first instruction of the scan line. The EOL bit in the WRITE and SKIP instructions indicate that this particular instruction is the last instruction of the scan line. An EOL flag from the FIFO along with the last DWORD for the scan line coincide with finishing the last instruction of the scan line. If the FIFO EOL condition occurs early, then the current instruction and all instructions leading up to the one that contains the EOL flag are aborted. If there is only one instruction to process the line, both SOL and EOL bits will be set. WRITE, WRITEC and SKIP control the processing of active pixel data stored in the FIFO. These three instructions alone control the sequence of packed mode data written to target memory on a byte resolution basis. The WRITEC instruction does not supply a target address. Instead, it relies on continuing from the current DMA pointer contained in the target address counter. This value is updated and kept current even during SKIP mode or FIFO overruns. However, WRITEC cannot be used to begin a new line, i.e. this instruction cannot have the SOL bit set. WRITE123, WRITE1S23, and SKIP123 control the processing of active pixel data stored in the FIFOs. These three instructions alone control the sequence of planar mode data written to target memory on a byte resolution basis. The WRITE1S23 instruction supports further decimation of chroma on a line basis. For each of these instructions, the same number of bytes will be processed from FIFO2 and FIFO3. The JUMP instruction is useful for repeating the same even/odd program for every frame or switching to a new program when the sequence needs to be changed without interrupting the pixel flow. The SYNC instruction is used to synchronize the RISC program and the pixel data stream. The DMA controller achieves this through the use of the status bits in DWORD0 of the SYNC instruction, and by matching them to the four FIFO status bits provided along with the pixel data. Once the DMA controller has matched the status bits between the FIFO and the RISC instruction, it proceeds with outputting data. Prior to establishing synchronization, the DMA controller reads and discards the FIFO data. Opcodes 0000 and 1111 are reserved to detect instruction errors. If these opcodes or the other unused opcodes are detected, an interrupt will be set. The DMA Controller will stop processing until the RISC program is re-enabled. This also applies to SYNC instructions specifying unused or reserved status codes. Detecting RISC instruction errors is useful for detecting software errors in programming, or ensuring that the DMA Controller is following a valid RISC sequence. In other words, it ensures that the program counter is not pointing to the wrong location. All unused/reserved bits in the instruction DWORDs must be set to zero.
54
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
Complex Clipping
It is necessary to be able to clip the video image before it is put onto the PCI bus when writing video data directly into on-screen display memory. The BT848 supports complex clipping of the video image for those applications which require the displayed video picture to be occluded by graphics objects such as pull-down menu, overlaying graphics window, etc. Typically, a target graphics frame buffer controller cannot provide overlay control for the video pixel data stream when it being provided by a PCI bus master peripheral to the graphics PCI host interface. The BT848 implements clipping by blocking the video image as it is being put onto the PCI bus in the areas where graphics are to be displayed, that is, where graphics objects are "overlaying" the video image. The BT848 cuts out portions of the video image so that it can "inlay" or fit around the displayed graphics objects. A clip list is provided through the graphics system DirectDRAW Interface (DDI) provider to the BT848 device driver software to indicate the areas of the display where the video image is to be occluded. The BT848 driver software interprets the clip list and generates a RISC program that blocks writing of video pixels that are to be occluded. This is illustrated in Figure 24.
Figure 24. Example of BT848 Performing Complex Clipping
System DRAM Y Cr Cb
Write #Bytes @ Line 0 ... Write #B @ L40, Skip #B, Wr #B @ L40 ... SYNC VRO Write123 #B @ Y, #B @ Cr, #B @ Cb ... SYNC VRE JUMP
Graphics Controller Frame Buffer Video in a Window Odd Field Prog Packed RGB Dialog Box
Even Field Prog Planar 4:2:2
CPU
Host Bridge PCI Bus
BT848
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L848A_A
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FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
Executing Instructions
Once the DMA controller has achieved synchronization between the FIFO and the RISC program, it proceeds with executing the RISC instructions. The data in the FIFO will be aligned with the data bytes expected by the RISC instructions. The DMA controller reads RISC instructions and performs burst writes from the FIFO. The DMA controller can be programmed to wait for 4, 8, 16, or 32 DWORDs in the FIFO before executing a WRITE instruction. Setting this FIFO trigger point optimizes the bus efficiency, by not allowing the DMA controller to access the bus every time a DWORD enters the FIFO. However, the FIFO trigger point is ignored in the case where the DMA controller is near the end of an instruction and the number of DWORDs left to transfer is less than the number of DWORDS in the FIFO. By allowing the instruction to complete, even if the FIFO is below its trigger point, the RISC instructions can be flushed sooner for every scan line. Otherwise, the DMA controller may have to wait for many scan lines before the required number of DWORDs are present in the FIFO, especially when capturing highly scaled down images. There may be several horizontal lines before another DWORD enters the FIFO. The FIFO trigger point is ignored by the DMA controller during all SKIP instructions. In the planar mode, the trigger points for the FIFOs should be set to the same level, even though the luma data is being stored in the Y FIFO at least twice as fast the chroma data is being stored in the Cr and Cb FIFOs. This ensures that the Y FIFO will be selected first to burst data onto the PCI bus. When the initiator is disconnected from the PCI bus while in the planar mode, it is essential to regain control of the bus as soon as possible and to deliver any queued DWORDs. The DMA controller will ignore the FIFO trigger point as it needs to empty the FIFO immediately, otherwise it may not have a chance to empty the rest of the FIFOs before it has to relinquish the bus. This is not a concern in the packed mode because all three FIFOs are treated as one large FIFO. The DMA controller immediately stops burst data writes and RISC instruction reads when the PCI target detects a parity error while the PCI initiator is reading the instruction data. This condition also causes an interrupt. There will be cases where the BT848 PCI initiator cannot gain control of the PCI bus, and the DMA controller is not able to execute the necessary WRITE instructions. Instead of writing data to the bus, the DMA controller reads data out of the FIFO and discards the data. To the FIFO, it appears as if the DMA controller is outputting to the bus. This allows the FIFO over-runs to be handled gracefully, with minimal loss of data. The BT848 is not required to abort a whole scan during FIFO over-runs. The DMA controller keeps track of the data to the nearest byte, and is able to deliver the rest of the scan line in the case the FIFO over-run condition is cleared. The BT848 DMA controller is normally monitoring the FIFO Full counters (FFULL) to determine how full the FIFOs are. However, before the DMA controller begins a burst write operation to process a WRITE instruction, it is desirable to
FIFO Over-run Conditions
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BT848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
DMA Controller
have some headroom in the FIFO to allow for more data to enter, while the PCI initiator is waiting for the target to respond. Hence, the BT848 monitors the FIFO Almost Full (FAFULL) counts. The Difference between FFULL and FAFULL provides the necessary headroom to handle target latency. Table 12 shows the FIFO size and FIFO Full/Almost Full counts in units of DWORDs.
Table 12. FIFO Full/Almost Full Counts FIFO FIFO1 FIFO2 FIFO3 Total Size 70 35 35 140 FFULL 68 34 34 136 FAFULL 64 32 32 128
Prior to the DMA controller executing the address phase of a PCI write transaction to process a WRITE instruction, the FIFO count value must be below the FAFULL level. At all other times, the FIFOs must be maintained below the FFULL level. The FIFO counters for all three FIFOs are monitored for full/almost full conditions in both planar and packed modes. Once the DMA controller begins the PCI bus transaction, it has committed to a target DMA start address. If the FIFO overflows while it is waiting for the target to respond, then the initiator must terminate the transaction just after the target responds. This is due to the fact that the DMA controller will have to start discarding the FIFO data, since the target pointer and the data are out of sync. This terminating condition will be communicated to the BT848 device driver by setting an interrupt bit that indicates interfacing to unreasonably slow targets. If an instruction is exhausted while the FIFO is in an over-run condition, the BT848 DMA controller will continue discarding the FIFO data during the next pre-fetched instruction as well. If the DMA controller runs out of RISC instructions, the FIFO continues to fill up, and PCI bus access is still denied, then the DMA controller will continue discarding FIFO data for the remainder of that scan line. Once the BT848 DMA controller detects the EOL control bits from the FIFO, it will attempt to gain access to the PCI bus and resynchronize itself with the RISC instruction EOL status bits. However, if the DMA controller is not successful in getting control of the bus, it will keep track of the number of scan lines discarded out of the FIFO and will resynchronize itself with the RISC program based on the number of EOL control signals detected. The planar mode requires that the DMA controller give priority to the Y FIFO to be emptied first. In the case that there is a very long latency in getting access to the PCI bus, all three FIFOs will be almost full when the bus is finally granted. While bursting the Y data, the CrCb data is likely to overflow. Attempting to deliver data from each FIFO to the bus will yield poor bus performance. Preference is given to the Y FIFO to finish the burst write operation, and if Cr or Cb FIFOs each reach a full condition, then the DMA controller will discard their data in parallel to delivering the Y data.
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L848A_A
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FUNCTIONAL DESCRIPTION
DMA Controller
BT848/848A/849A
Single-Chip Video Capture for PCI
FIFO Data Stream Resynchronization
The BT848 DMA controller is constantly monitoring whether there is a mismatch between the amount of data expected by the RISC instruction and the amount of data being provided by the FIFO. The DMA controller then corrects for the mismatches and realigns the RISC program and the FIFO data stream. For example, if the FIFO contains a shorter video line that expected by the RISC instruction, the DMA controller detects the EOL control code from the FIFO earlier than expected. The DMA controller then aborts the rest of the RISC instructions until it detects the EOL control code from the RISC program. If the FIFO contains a longer video line than expected by the RISC instruction, the DMAC will not detect the EOL control code from the FIFO at the expected time. The DMAC will continue reading the FIFO data, however it will discard the additional FIFO data until it reaches the EOL control code from the FIFO. Similarly, if the FIFO provides a smaller number of scan lines per field than expected by the RISC program, the end of field control codes from the FIFO (VRE/VRO) will arrive early. The DMA controller then aborts all RISC instructions until the SYNC status codes from the RISC instruction match the end of field status codes from the FIFO. If the FIFO provides a larger number of scan lines per field than expected by the RISC program, the end of field control codes from the FIFO (VRE/VRO) will not arrive at the expected time. Again, the FIFO data is read by the DMAC and discarded until the SYNC status codes from the RISC instruction match the end of field status codes from the FIFO. The DMA controller manages all of the above error conditions, but the FIFO Data Stream Resynchronization interrupt bit will be set as well.
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ELECTRICAL INTERFACES
Input Interface
Analog Signal Selection The BT848 contains an on-chip 3:1 mux while the BT848A/849A includes an on-chip 4:1 mux. This mux can be used to switch between three composite sources or two composite sources and one S-video source. In the first configuration, connect the inputs of the mux (MUX0, MUX1 and MUX2) to the three composite sources. In the second configuration, connect two inputs to the composite sources and the other input to the luma component of the S-video connector. In both configurations the output of the mux (MUXOUT) should be connected to the input to the luma A/D (YIN) and the input to the sync detection circuitry (SYNCDET). The BT848A/849A does not require MUXOUT be connected to SYNCDET. When implementing S-video, the input to the chroma A/D (CIN) should be connected to the chroma signal of the S-video connector. Use of the multiplexer is not a requirement for operation. If digitization of only one video source is required, the source may be connected directly to YIN and SYNCDET. The multiplexer is not a break-before-make design. Therefore, during the multiplexer switching time it is possible for the input video signals to be momentarily connected together through the equivalent of 200 . The multiplexers cannot be switched on a real-time pixel-by-pixel basis. If the BT848 is configured to decode both NTSC and PAL/SECAM, the BT848 can be programmed to automatically detect which format is being input to the chip. Autodetection will select the proper clock source for the format detected, (if NTSC is detected, XTAL0 is selected; if PAL/SECAM is detected, XTAL1 is selected.) The BT848 determines the video source input to the chip by counting the number of lines in a frame. Based on the result, the format of the video is determined, and XT0 or XT1 is selected for the clock source. Automatic format detection will select the clock source, but it will not program the required registers.
Multiplexer Considerations
Autodetection of NTSC or PAL/SECAM Video
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ELECTRICAL INTERFACES
Input Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
Flash A/D Converters
The BT848 uses two on-chip flash A/D converters to digitize the video signals. YREF+, CREF+ and YREF-, CREF- are the respective top and bottom of the internal resistor ladders. The input video is always AC-coupled to the decoder. CREF- and YREF- are connected to analog ground. The voltage levels for YREF+ and CREF+ are controlled by the gain control circuitry. If the input video momentarily exceeds the corresponding REF+ voltage it is indicated by LOF and COF in the STATUS register. An internally generated clamp control signal is used to clamp the inputs of the A/D converter for DC restoration of the video signals. Clamping for both the YIN and CIN analog inputs occurs within the horizontal sync tip. The YIN input is always restored to ground while the CIN input is always restored to CLEVEL. CLEVEL must be set with an external resistor network so that it is biased to the midpoint between CREF- and CREF+. External clamping is not required because internal clamping is automatically performed (the BT848A and Bt849A do not require that CLEVEL be connected to a resistor network). Upon power-up, the status of the BT848's registers is indeterminate. The RST signal must be asserted to set the register bits to their default values. The BT848 device defaults to NTSC-M format upon reset. The REFOUT, CREF+ and YREF+ pins should be connected together as shown in Figure 25. In this configuration, the BT848 controls the voltage for the top of the reference ladder for each A/D. The automatic gain control adjusts the YREF+ and CREF+ voltage levels until the back porch of the Y video input generates a digital code 0x38 from the A/D. The BT848 has two pairs of pins, XT0I/XT0O and XT1I/XT1O, that are used to input a clock source. If both NTSC and PAL video are being digitized, both clock inputs must be implemented. The XT0 port is used to decode NTSC video and must be configured with a 28.63636 MHz source. The XT1 port is used to decode PAL video and must be configured with a 35.46895 MHz source. If the BT848 is configured to decode either NTSC or PAL but not both, then only one clock source must be provided to the chip and it must be connected to the XT0I/XT0O port. If a crystal input is not used, the crystal amplifiers are internally shut down to save power.
A/D Clamping
Power-up Operation
Automatic Gain Controls
Crystal Inputs and Clock Generation
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
Input Interface
Crystals are specified as follows: * 28.636363 MHz or 35.468950 MHz * Third overtone * Parallel resonant * 30 pF load capacitance * 50 ppm * Series resistance 40 or less The following crystals are recommended for use with the BT848: 1 Standard Crystal (818) 443-2121 2BAK28M636363GLE30A 2BAK35M468950GLE30A 2 MMD (714) 444-1402 A30AA3-28.63636 MHz A30AA3-35.46895 MHz 3 GED (619) 591-4170 PKHC49-28.63636-.030-005-40R, 3rd overtone crystal PKHC49-35.46895-.030-005-40R, 3rd overtone crystal 4 M-Tron (800) 762-8800 MP-1 28.63636, 3rd overtone crystal MP-1 35.46895, 3rd overtone crystal 5 Monitor (619) 433-4510 MM49X3C3A-28.63636, 3rd overtone crystal MM49X3C3A-35.46895, 3rd overtone crystal 6 CTS (815) 786-8411 R3B55A30-28.63636, 3rd overtone crystal R3B55A30-35.46895, 3rd overtone crystal 7 Fox (813) 693-0099 HC49U-28.63636, 3rd overtone crystal HC49U-35.46895, 3rd overtone crystal The two clock sources may be configured with either single-ended oscillators, fundamental cut crystals or third overtone mode crystals, parallel resonant. If single-ended oscillators are used they must be connected to XT0I and XT1I. The clock source options and circuit requirements are shown in Figure 26. The clock source tolerance should be 50 parts-per-million (ppm) or less. Devices that output CMOS voltage levels are required. The load capacitance in the crystal configurations may vary depending on the magnitude of board parasitic capacitance. The BT848 is dynamic, and, to ensure proper operation, the clocks must always be running, with a minimum frequency of 28.636363 MHz.
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L848A_A
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ELECTRICAL INTERFACES
Input Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 25. Typical External Circuitry
VAA 2 K REFOUT Not Required on BT848A/849A YREF+ CREF+ VNEG VPOS AGCCAP 330 pF 330 pF 0.1 F 75 VAA Optional Anti-aliasing Filter 3.3 H 0.1 F MUX(0-3)
0.1 F JTAG 30 K CLEVEL 30 K 0.1 F I2C
YREF- CREF- Not Required on BT848A/849A 2.2 H
0.1 F MUX0 XT1O 75 75 Termination XT1I 0.1 F MUX1 75 0.1 F 0.1 F MUX2 75 XT0I 22 pF XT0O 28.63636 MHz 1 M 22 pF 35.46895 MHz 1 M 0.1 F
33 pF
2.7 H
33 pF
The MUX3 input is only available on the BT848A and Bt849A 0.1 F MUX3 MUXOUT 75 YIN 0.1 F 0.1 F CIN 75 AC Coupling Capacitor 1 M Not Required on BT848A/849A SYNCDET Analog Ground 0.1 F Digital Ground
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
Input Interface
Figure 26. Clock Options
XT0O
XT1O
XT0I 28.63636 MHz 1 M 22 pF 0.1 F 2.7 H Osc XT0I XT0I 28.63636 MHz 1 M 47 pF 47 pF
XT1I 35.46895 MHz 1 M 22 pF 0.1 F 2.2 H
33 pF
33 pF
NTSC Third Overtone Mode Crystal Oscillator
PAL/SECAM Third Overtone Mode Crystal Oscillator
28.63636 MHz
NTSC Single-ended Oscillator
NTSC Fundamental Crystal Oscillator
XT0O XT0O 47 pF
XT1O
Osc
PAL/SECAM Single-ended Oscillator
PAL/SECAM Fundamental Crystal Oscillator
XT1I XT1I 35.46895 MHz 1 M 47 pF
35.46895 MHz
XT1O
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ELECTRICAL INTERFACES
Input Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
Single Crystal Operation (BT848A/849A Only)
The BT848A/849A includes an internal phase locked loop that may be used to decode NTSC and PAL using only a single crystal. When using the PLL, a 28.636363 MHz, 50 ppm, fundamental (or third overtone) crystal must be connected to XT0. This clock is used to generate the CLKx2 frequency via the following equation: Frequency = (F_input / PLL_X) * PLL_I.PLL_F/PLL_C where F_input = 28.63636 MHz (50 ppm) PLL_X = Reference pre-divider PLL_I = Integer input PLL_F = Fractional input PLL_C = Post divider These values should be programmed as follows to generate PAL frequencies: PAL (CLKx2 = 35.46895 MHz) PLL_X = 1 PLL_I = 0x0E PLL_F = 0xDCF9 PLL_C = 0 The PLL can be put into low power mode by setting PLL_I to zero. For NTSC operation PLL_I should be set to zero. In this mode, the correct clock frequency is already input to the system and the PLL is shut down. An out of lock or error condition is indicated by the PLOCK bit in the PSTATUS register. When using the PLL to generate the required NTSC and PAL clock frequencies the following sequence must be followed: Initially, TGCKI bits in the TGCTRL register must be programmed for normal operation of the XTAL ports. After the PLL registers are programmed, the PLOCK bit in the DSTATUS register must be polled until it has been verified that the PLL has attained lock (approximately 500 ms). At that point the TGCKI bits are set to select operation via the PLL.
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
Input Interface
2X Oversampling and Input Filtering
Digitized video needs to be bandlimited in order to avoid aliasing artifacts. Because the BT848 samples the video data at 8xFsc (over twice the normal rate), no filtering is required at the input to the A/Ds. The analog video needs to be band limited to 14.32 MHz in NTSC and 17.73 MHz in PAL/SECAM mode. Normal video signals do not require additional external filtering. However, if noise or other signal content is expected above these frequencies, the optional anti-aliasing filter shown in Figure 25 may be included in the input signal path. After digitization, the samples are digitally low pass filtered and then decimated to 4xFsc. The response of the digital low pass filter is shown in Figure 27. The digital low pass filter provides the digital bandwidth reduction to limit the video to 6 MHz.
Figure 27. Luma and Chroma 2x Oversampling Filter
PAL/SECAM NTSC
NTSC
PAL/SECAM
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ELECTRICAL INTERFACES
PCI Bus Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
PCI Bus Interface
The PCI local bus is an architectural, timing, electrical, and physical interface that allows the BT848 to interface to the local bus of a host CPU. BT848 is fully compliant with PCI Rev. 2.1 specifications. The supported bus cycles for the PCI initiator and target are as follows: * * Memory Read Memory Write
The supported bus cycles for the PCI target only are as follows: * * * * * Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate
Memory Write and Invalidate is treated in the same manner as Memory Write. Memory Read Multiple and Memory Read Line are treated in the same manner as Memory Read. The unsupported PCI bus features are as follows: * * * * * * 64-bit Bus Extension I/O Transactions Special, Interrupt Acknowledge, Dual Address Cycles Locked Transactions Caching Protocol Initiator Fast Back-to-back Transactions to Different Targets
As a PCI master, BT848 supports agent parking, AD[31:0], CBE[3:0], and PAR driven if GNT is asserted and follows an idle cycle (regardless of the state of BUS MASTER). All bus commands accepted by the BT848 as a target require a minimum of 3 clock cycles. This allows for a full internal clock cycle address decode time (medium devsel timing) and a registered state machine interface. Write burst transactions can continue with zero wait state performance on the fourth clock cycle and onward (unless writing to video decoder/scaler registers). All read burst transactions contain 1 wait-state per data phase. A block diagram of the PCI interface is shown in Figure 28.
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
PCI Bus Interface
Figure 28. PCI Block Diagram
FIFO Data DMA Controller PCI Initiator
PCI Control Signals
FIFO Control Signals
PCI Config. Registers
I
2C
Master
Local Registers GPIO
Video Decoder Interrupts
Interrupts CLK
INTA
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PCI Bus Interface
PCI Target
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L848A_A
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ELECTRICAL INTERFACES
General Purpose I/O Port
BT848/848A/849A
Single-Chip Video Capture for PCI
General Purpose I/O Port
The BT848 provides a 24-bit wide general purpose I/O port. There are two modes of operation for the GPIO port: normal mode and synchronous pixel interface (SPI) mode. In the normal mode, the GPIO port is used as a general purpose port enabling 24-bits of data to be input or output (Figure 29). In the SPI input mode, the GPIO port can be used to input the video data from an external video decoder and bypass the BT848's video decoder block (Figure 30). In the SPI output mode, the output of the BT848's video decoder can be passed over the GPIO bus (Figure 31), while being utilized by the rest of the BT848 circuitry. In addition to the 24 I/O bits, the GPIO port includes an interrupt pin, and a write enable pin. The GPINTR signal sets the bit in the interrupt register and causes an interrupt condition to occur. The GPWE signal enables sampling of the data on the GPIO port and places the data in an internal GPIO register. The polarity of the GPWE pin is programmable. The SPI output mode is automatically enabled if GPWE is sampled high and GPINTR is sampled low upon release of the RST pin. This overrides the GPIOMOD bits in the GPIO/DMA control register and can only be returned to register control by assertion of the RST pin while GPWE and GPINTR are in any other states than high and low respectively. Care must be taken to ensure the state of GPWE and GPINTR are configured correctly for the desired use of the GPIO pins. Internal pullups are provided on both pins.
Figure 29. GPIO Normal Mode Video Decoder Video Data Format Converter Local Registers
GPIO Port 24 Bits of General I/O
Scaler
FIFO
DMA Controller and PCI Initiator
External Circuitry
Figure 30. GPIO SPI Input Mode Video Decoder Video Data Format Converter Local Registers
GPIO Port
Scaler
FIFO
DMA Controller and PCI Initiator
External Video Decoder
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
General Purpose I/O Port
Figure 31. GPIO SPI Output Mode
Video Decoder
Scaler
Video Data Format Converter
FIFO
DMA Controller and PCI Initiator
Local Registers
GPIO Port BT848 Video Decoder Output
External Circuitry
GPIO Normal Mode
In the GPIO normal mode, each of the general purpose I/O pins can be programmed individually. An internal register (GPOE) can be programmed to enable the output buffers of the pins selected as outputs. The contents of the GPDATA register are put on the enabled GPIO output pins. In the case where the GPIO pins are used as general purpose input pins, the contents of the GPIO data register are ignored and the signals on the GPIO bus pins are read through a separate register. The GPIO normal mode allows PCI burst transfers by providing a 64-DWORD contiguous address space. This allows the PCI bus to burst 64 DWORDs without having to resend the address for each DWORD. The 32-bit PCI DWORD is truncated and only the lower 24 bits are output over the GPIO port. This in effect provides a high speed output bus interface for non-PCI external devices. In the SPI input and output modes, the GPIO pins are mapped as shown in Table 13. Note that the GPIO signal names correspond to those of a stand-alone video decoder such as the Bt819A or Bt829. A separate clock pin (GPCLK) is used for the clock signal. In the SPI input mode, the GPCLK signal is used to input an external clock signal. In the SPI output mode, the GPCLK signal is used to output the BT848's CLKx1 (4*Fsc). Figure 33 and Figure 32 show the basic timing relationships for the SPI output mode. In the SPI input mode, it is assumed that a video decoder similar to the Bt819A or Bt829 is connected to the GPIO port. The YCrCb 4:2:2 pixel stream follows the CCIR recommendation when the RANGE bit in the Output Format register is set to a logical zero. CCIR 601 specifies that nominal video will have Y values ranging from 16 to 235, and the Cr and Cb values will range from 16 to 240. However, excursions outside this range are allowed to handle non-standard video. The only mandatory requirement is that 0 and 255 be reserved for timing information.
GPIO SPI Modes
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General Purpose I/O Port
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 13. Synchronous Pixel Interface (SPI) GPIO Signals GPIO [23] Signal HRESET Description A 64-clock-long active low pulse. It is output following the rising edge of CLKx1. The falling edge of HRESET indicates the beginning of a new video line. An active low signal that is at least two lines long (for non-VCR sources, VRESET is normally six lines long). It is output following the rising edge of CLKx1. The falling edge of VRESET indicates the beginning of a new field of video output. The falling edge of VRESET lags the falling edge of HRESET by two clock cycles at the start of an odd field. At the start of even fields, the falling edge of VRESET is in the middle of a scan line, horizontal count (HPIXEL/2)+1, on scan line 263 for NTSC and scan line 313 for PAL. An active high signal that indicates the beginning of the active video and is output following the rising edge of CLKx1. The HACTIVE flag is used to indicate where nonblanking pixels are present. The start and the end of the HACTIVE signal can be adjusted by programming the HDELAY and HACTIVE registers. An active high pixel qualifier that indicates whether or not the associated pixel is valid. DVALID is independent of the HACTIVE and VACTIVE signals. DVALID indicates which pixels are valid. DVALID will toggle high outside of the active window, indicating a valid pixel outside the programmed active region. An active high pulse that indicates when Cb data is being output on the chroma stream. During invalid pixels, CBFLAG holds the value of the last valid pixel. When high, indicates that an even field (field 2) is being output; when low it indicates that an odd field (field 1) is being output. The transition of FIELD is synchronous with the end of active video (i.e. the trailing edge of ACTIVE). The same information can also be derived by latching the HRESET signal with VRESET. An active high signal that indicates the beginning of the active video and is output following the rising edge of CLKx1. The VACTIVE flag is used to indicate where nonblanking pixels are present. The start and the end of the VACTIVE signal can be adjusted by programming the VDELAY and VACTIVE registers. An active high signal that indicates the beginning and end of the vertical blanking interval. The end of VBISEL will adjust accordingly when VDELAY is changed. Digital pins for the luminance component of the video data stream. Digital pins for the chrominance component of the video data stream Pin Number 82
[22]
VRESET
83
[21]
HACTIVE
84
[20]
DVALID
85
[19]
CBFLAG
86
[18]
FIELD
87
[17]
VACTIVE
88
[16]
VBISEL
89
[15:8] [7:0]
Y[7:0] CrCb[7:0]
92-99 110-117
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BT848/848A/849A
Single-Chip Video Capture for PCI
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General Purpose I/O Port
Figure 32. Video Timing in SPI Mode BEGINNING OF FIELDS 1, 3, 5, 7 HRESET
(1)
VRESET
FIELD
HACTIVE
VACTIVE
VBISEL
2-6 SCAN LINES
VDELAY/2 SCAN LINES
BEGINNING OF FIELDS 2, 4, 6, 8 HRESET
VRESET
FIELD
HACTIVE
VACTIVE
VBISEL
2-6 SCAN LINES
VDELAY/2 SCAN LINES
Notes: (1). HRESET precedes VRESET by two clock cycles at the beginning of fields 1, 3, 5 and 7 to facilitate external field generation. 2. ACTIVE pin may be programmed to be composite ACTIVE or horizontal ACTIVE. 3. FIELD transitions with the end of horizontal active video defined by HDELAY and HACTIVE.
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General Purpose I/O Port
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 33. Basic Timing Relationships for SPI Mode Y[7:0] CRCB[7:0] DVALID ACTIVE
GPCLK
CBFLAG
Digital Video in Support (BT848A/849A Only)
This section describes how to use the BT848A/849A with a digital camera. The GPIO port can be configured to accept general digital data streams. The BT848A/849A contains an SRAM based state machine that isolates the digital video input events from the internal decoder timing. It allows the digital video input H & V events to synchronize the sequencer and the programmable output events to be positioned where needed to synchronize the decoder. A 20 x 20 SRAM is used to store H & V count values and signal values for generation of timing events. The SRAM is programmed once for interfacing to a given digital video input standard. The address for the SRAM is a 20-bit shift register with reset and advance inputs. The SRAM is written in sequence, in byte-mode, after a reset. Then the SRAM will function normally in video mode. The addr s/r will be advanced every time the H or V value compares exactly to the HC or VC counters, or reset when the HRST signal output is active and the HC reaches the final H value. These register settings can be found in the Control Register Digital Video In Support (BT848A/849A only). The digital input port on the BT848A and Bt849A provides flexibility for interfacing to video standards. Software for programming the BT848A/Bt849A is included in the development kit for interfacing to the following standards. Table 14 provides the alternate pin definitions when using the digital video-in mode.
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
General Purpose I/O Port
Table 14. Pin Definition of GPIO Port When Using Digital Video-In Mode GPIO [23] [22] [21] [20] [19] [18] [17] [16] [9] [8] [7:0] CLKx1 FIELD VACTIVE VSYNC HACTIVE HSYNC Composite ACTIVE Composite SYNC VSYNC/FIELD HSYNC DATA Cb, Yo, Cr, Y, ... Video data input at GPCLK = CLKx2 rate. Input signals for synchronizing to input video. Signal Description Output signals for synchronizing to input video. Pin Number 82 83 84 85 86 87 88 89 98 99 110-117
CCIR656
This is a 27 MB/s interface in the form of Cb, Y, Cr, Y, Cb, etc. In this sequence, the word sequence Cb, Y, Cr, refers to co-sited and color-difference samples and the following word, Y, corresponds to the next luminance sample. In this interface there are two timing reference codes (SAV and EAV) that occur at the start and end of active video. These 4-byte codes occur at the outside boundaries of the active video. A 720 pixels in the active video line corresponds to 1440 samples. 1448 bytes make up a video data block (one line of video with reference codes). The full video line consists of 1716 bytes (in 525 line systems) and 1728 (in 626 line systems). The line is broken into two parts. The first is blanking, which consists of the front porch, hsync, and back porch, 276 (288 in 635 line systems) bytes from EAV through SAV. The leading edge of hsync occurs 32 (24 in 625 line systems) bytes after the start of the digital line. The field interval is aligned to this leading edge of hsync. See Figure 34 for a diagram on the interface. For a full reference on this standard please refer to the CCIR (The International Radio Consultive Committee) standards directly.
Figure 34. CCIR 656 or ByteStream Interface to Digital Input Port
Clock CCIR 656 or ByteStream Video Generator (ex. Bt829)
GPCLK BT848A/849A
DATA[7:0]
8
GPIO[7:0]
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L848A_A
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ELECTRICAL INTERFACES
General Purpose I/O Port
BT848/848A/849A
Single-Chip Video Capture for PCI
Modified SMPTE-125
This interface is the same as CCIR 656 but the clock runs at 24.54 MHz, and there are 640 active pixels on a 780 pixel line. This clock rate difference provides simple interface for digital cameras from Silicon Vision and Logitech.
ByteStream
The BT848A and Bt849A may also accept data as defined in the ByteStream video interface standard. This interface is completely defined in the Bt829 video decoder datasheet. See Figure 34 for a diagram on this interface. Additional digital interfaces may be implemented by contacting the Rockwell applications group.
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
I2C Interface
I2C Interface
The Inter-Integrated Circuit (I2C) bus is a two-wire serial interface. Serial clock and data lines, SCL and SDA, are used to transfer data between the bus master and the slave device. The BT848 implements a single master I2C system, allowing no other I2C master devices, but many slaves may be in the system. The timing for the bus will be derived from the PCI clock which may be 33 MHz or slower. BT848's fixed divide by 16 divider provides a timing resolution of 0.48 S. A programmable register determines the additional divide ratio to divide the clock down to 100 KHz or slower rates. The formula for the I2C bit rate is as follows: PCI Clock Rate Bit Rate = -----------------------------------------------------4 x ( 16 x I2CDIV + 4 ) where: I2CDIV = Register bits in the I2C Data/Control Register
An I2C slave may slow down the data transfer rate even further by inserting wait states. The relationship between SCL and SDA is decoded to provide both a start and stop condition on the bus. To initiate a transfer on the I2C bus, the master must transmit a start pulse to the slave device. This is accomplished by taking the SDA line low while the SCL line is held high. The master should only generate a start pulse at the beginning of the cycle, or after the transfer of a data byte to or from the slave. To terminate a transfer, the master must take the SDA line high while the SCL line is held high. The master may issue a stop pulse at any time during an I2C cycle. Since the I2C bus will interpret any transition on the SDA line during the high phase of the SCL line as a start or stop pulse, care must be taken to ensure that data is stable during the high phase of the clock. This is illustrated in Figure 35.
Figure 35. The Relationship between SCL and SDA
SCL
SDA
START
STOP
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L848A_A
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I2C Interface
ELECTRICAL INTERFACES
BT848/848A/849A
Single-Chip Video Capture for PCI
An I2C write transaction consists of sending a START signal, 2 or 3 bytes of data (checking for a receiver acknowledge after each byte), and a STOP signal. The write data is supplied from a 24-bit register with bytes I2CDB0, I2CDB1, and I2CDB2. This 24-bit register is shifted left to provide data serially, with the MSB as the first bit. An I2C write occurs when the R/W bit in the I2CDB0[0] is set to a logical low. The system driver can select to write 2 or 3 bytes of data by selecting the appropriate value for I2CW3B bit. An I2C read transaction consists of sending a START signal, 1 byte of data (checking for a receiver acknowledge), reading 1 data byte from the slave, sending the master NACK, and sending the STOP signal. The data read is shifted into the I2CDB2 register. An I2C read occurs when the R/W bit in the I2CDB0[0] is set to a logical one (Figure 36). When the read or write operation is completed, BT848 sends an interrupt over the PCI bus to the host controller. The status bit RACK will indicate whether the operation completed successfully with the correct number of slave acknowledges. In the case where direct control of the I2C bus lines is desired, the BT848 device driver can disable the I2C hardware control and can take software control of the SCL and SDA pins. This is useful in applications where the I2C bus is used for general purpose I/O or if a special type of I2C operation (such as multi-mastering) needs to be implemented.
Figure 36. I2C Typical Protocol Diagram DATA WRITE
S CHIP ADDR A SUB-ADDR 8 BITS A DATA A P
S P A NA
= START = STOP = ACKNOWLEDGE = NON ACKNOWLEDGE FROM BT848 TO SLAVE
DATA READ
S CHIP ADDR A DATA NA P
FROM SLAVE TO BT848
For detailed information on the I2C bus, refer to "The I2C-Bus Reference Guide," reprinted by Brooktree.
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BT848/848A/849A
Single-Chip Video Capture for PCI
ELECTRICAL INTERFACES
JTAG Interface
JTAG Interface
Need for Functional Verification As the complexity of imaging chips increases, the need to easily access individual chips for functional verification is becoming vital. The BT848 has incorporated special circuitry that allows it to be accessed in full compliance with standards set by the Joint Test Action Group (JTAG). Conforming to IEEE P1149.1 "Standard Test Access Port and Boundary Scan Architecture," the BT848 has dedicated pins that are used for testability purposes only. JTAG's approach to testability utilizes boundary scan cells placed at each digital pin and digital interface (a digital interface is the boundary between an analog block and a digital block within the BT848). All cells are interconnected into a boundary scan register that applies or captures test data to be used for functional verification of the integrated circuit. JTAG is particularly useful for board testers using functional testing methods. JTAG consists of five dedicated pins comprising the Test Access Port (TAP). These pins are Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI), Test Data Out (TDO) and Test Reset (TRST). The TRST pin will reset the JTAG controller when pulled low at any time. Verification of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these five TAP pins. With boundary scan cells at each digital interface and pin, the BT848 has the capability to apply and capture the respective logic levels. Since all of the digital pins are interconnected as a long shift register, the TAP logic has access and control of all the necessary pins to verify functionality. The TAP controller can shift in any number of test vectors through the TDI input and apply them to the internal circuitry. The output result is scanned out on the TDO pin and externally checked. While isolating the BT848 from other components on the board, the user has easy access to all BT848 digital pins and digital interfaces through the TAP and can perform complete functionality tests without using expensive bed-of-nails testers.
JTAG Approach to Testability
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L848A_A
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ELECTRICAL INTERFACES
JTAG Interface
BT848/848A/849A
Single-Chip Video Capture for PCI
Optional Device ID Register
The BT848 has the optional device identification register defined by the JTAG specification. This register contains information concerning the revision, actual part number, and manufacturers identification code specific to Brooktree. This register can be accessed through the TAP controller via an optional JTAG instruction. Refer to Table 15.
Table 15. Device Identification Register Version Part Number Manufacturer ID
XXXX0000001101010000000110101101 0 4 Bits 0848, 0x0350 16 Bits 0x0D6 11 Bits
Verification with the Tap Controller
A variety of verification procedures can be performed through the TAP controller. With a set of four instructions, the BT848 can verify board connectivity at all digital interfaces and pins. The instructions are accessible by using a state machine standard to all JTAG controllers and are: Sample/Preload, Extest, ID Code, and Bypass (see Figure 37). Refer to the IEEE P1149.1 specification for details concerning the Instruction Register and JTAG state machine. Brooktree has created a BSDL with the AT&T BSD Editor. Should JTAG testing be implemented, a disk with an ASCII version of the complete BSDL file may be obtained by calling 1-800-2Bt Apps.
NOTE:
Not all PCs drive the PCI bus TRST pin. In these computers, if the TRST pin on the BT848 board is connected to TRST on the PCI bus (which is not driven) there is a potential that the BT848 may power-up in an undefined state. In these designs the TRST pin on the BT848 must be grounded (disabling JTAG).
Figure 37. Instruction Register
TDI
TDO
EXTEST Sample/Preload ID Code Bypass
0 0 0 1
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PC BOARD LAYOUT CONSIDERATIONS
The layout should be optimized for lowest noise on the BT848 power and ground lines by shielding the digital inputs/outputs and providing good decoupling. The lead length between groups of power and ground pins should be minimized to reduce inductive ringing. Ground Planes The ground plane area should encompass all BT848 ground pins, voltage reference circuitry, power supply bypass circuitry for the BT848, the analog input traces, any input amplifiers, and all the digital signal traces leading to the BT848. The BT848 has digital grounds (GND) and analog grounds (AGND and VNEG). The layout for the ground plane should be such that the two planes are at the same electrical potential, but they should be isolated from each other in the areas surrounding the chip. Also, the return path for current should be through the digital plane. See Figure 38.
Figure 38. Example Ground Plane Layout
Analog Ground 1 121
BT848
41 Digital Ground 81
Ground Return (i.e. PCI Bus Connection)
Brooktree
Circuit board edge
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PC BOARD LAYOUT CONSIDERATIONS
Power Planes
BT848/848A/849A
Single-Chip Video Capture for PCI
Power Planes
The power plane area should encompass all BT848 power pins, voltage reference circuitry, power supply bypass circuitry for the BT848, the analog input traces, any input amplifiers, and all the digital signal traces leading to the BT848. The BT848 has digital power (VDD) and analog power (VAA and VPOS). The layout for the power plane should be such that the two planes are at the same electrical potential, but they should be isolated from each other in the areas surrounding the chip. Also, the source path for current should be through the digital plane. This is the same layout as shown for the ground plane (Figure 38). When using a regulator, circuitry must be included to ensure proper power sequencing. The circuitry shown in Figure 39 should help in this regard. The bypass capacitors should be installed with the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. These capacitors should also be placed as close as possible to the device. Each group of VAA and VDD pins should have a 0.1 F ceramic bypass capacitor to ground, located as close as possible to the device. Additionally, 10 F capacitors should be connected between the analog power and ground planes, as well as between the digital power and ground planes. These capacitors are at the same electrical potential, but are physically separate, and provide additional decoupling by being physically close to the BT848 power and ground planes. See Figure 40 for additional information about power supply decoupling. The digital signals of the BT848 should be isolated as much as possible from the analog signals and other analog circuitry. Also, the digital signals should not overlay the analog power plane. Any termination resistors for the digital signals should be connected to the digital PCB power and ground planes. Long lengths of closely-spaced parallel video signals should be avoided to minimize crosstalk. Ideally, there should be a ground line between the video signal traces driving the YIN and CIN inputs. Also, high-speed TTL signals should not be routed close to the analog signals to minimize noise coupling.
Supply Decoupling
Digital Signal Interconnect
Analog Signal Interconnect
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BT848/848A/849A
Single-Chip Video Capture for PCI
PC BOARD LAYOUT CONSIDERATIONS
Latch-up Avoidance
Latch-up Avoidance
Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more than 0.5 V, or falling below the GND pins by more than 0.5 V. Latch-up can also occur if the voltage on any power pin exceeds the voltage on any other power pin by more than 0.5 V. In some cases, devices with mixed signal interfaces, such as the BT848, can appear more sensitive to latch-up. In reality, this is not the case. However, mixed signal devices tend to interact with peripheral devices such as video monitors or cameras that are referenced to different ground potentials, or apply voltages to the device prior to the time that its power system is stable. This interaction sometimes creates conditions amenable to the onset of latch-up. To maintain a robust design with the BT848, the following precautions should be taken: * Apply power to the device before or at the same time as the interface circuitry. * Do not apply voltages below GND-0.5 V, or higher than VAA+0.5 V to any pin on the device. Do not use negative supply op-amps or any other negative voltage interface circuitry. All logic inputs should be held low until power to the device has settled to the specified tolerance. * Connect all VDD, VAA and VPOS pins together through a low impedance plane. * Connect all GND, AGND and VNEG pins together through a low impedance plane.
Figure 39. Optional Regulator Circuitry SYSTEM POWER (+12 V) IN GND
DIODES MUST HANDLE
VAA,VDD (+5 V) OUT
SYSTEM POWER (+5 V)
GROUND SUGGESTED PART NUMBERS: REGULATOR TEXAS INSTRUMENTS
THE CURRENT REQUIREMENTS OF THE
BT848 AND THE
PERIPHERAL CIRCUITRY
A78 MO5M
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L848A_A
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PC BOARD LAYOUT CONSIDERATIONS
Latch-up Avoidance
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 40. Typical Power and Ground Connection Diagram and Parts List
PCI
VIO
VDDP
C3
+5V C4 + Analog Area
VDD, VDDG
VAA, VPOS C6 + C1 AGND, VNEG C5 + C2
BT848/848A/849A
Ground
GND
Location C1-3(1) C4-6
(2)
Description 0.1 F ceramic capacitor 10 F tantalum capacitor
Vendor Part Number Erie RPE112Z5U104M50V Mallory CSR13G106KM
Notes: (1). A 0.1 F capacitor should be connected between each group of power pins and ground as close to the device as possible, (ceramic chip capacitors are preferred). (2). The 10 F capacitors should be connected between the analog supply and the analog ground, as well as the digital supply and the digital ground. These should be connected as close to the BT848 as possible. 3. These vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the BT848.
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CONTROL REGISTER DEFINITIONS
BT848 supports two types of address spaces. The configuration address space includes the pre-defined PCI configuration registers, while the memory address space includes all the local registers used by BT848 to control the remaining portions of the device. Both the PCI configuration address space and the memory address space start at memory location 0x00. The PCI-based system distinguishes the two address spaces based on the Initialization Device Select, PCI address and command signals that are issued during the appropriate software commands.
PCI Configuration Space
The PCI configuration space defines the registers used to interface between the host and the PCI local bus. This section defines the organization of the registers within the 64 byte predefined header portion of the configuration space. Figure 41 shows the configuration space header. For details on the PCI bus, refer to the PCI Local Bus Specification, Revision 2.1.
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L848A_A
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CONTROL REGISTER DEFINITIONS
PCI Configuration Space
BT848/848A/849A
Single-Chip Video Capture for PCI
Figure 41. PCI Configuration Space Header 31 Device ID Status Class Code Reserved Header Type 0 Latency Timer 16 15 Vendor ID Command Revision ID Reserved 0 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Reserved 0x20 0x24 Reserved Reserved Reserved Reserved Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x28 0x2C 0x30 0x34 0x38 0x3C
Base Address 0 Register Reserved
The BT848 is a single-function device, and only supports type 0 configuration cycles. The configuration space registers are stored in dwords and defined by byte addresses. Therefore a register one byte in length can have a bit definition other than [7:0] (for example [31:24]), depending on its location in the configuration space. For a discussion on configuration cycle addressing, refer to Section 3.6.4.1 of the PCI Local Bus Specification, Revision 2.1. The configuration space is accessible at all times even though it is not typically accessed during normal operation. These registers are normally accessed by the Power On Self Test (POST) code and by the device driver during initialization time. Software will however read the status register during normal operation when a PCI bus error occurs and is detected by BT848. The Configuration Space is accessed when the Initialization Device Select (IDSEL) pin is high, and AD[1:0] = 00, otherwise the cycle is ignored. The configuration register addresses are each offset by 4, since AD[1:0] = 00. BT848 supports burst R/W cycles. Write operations to reserved, unimplemented, or read-only registers/bits complete normally with the data discarded. Read accesses to reserved or unimplemented registers/bits return a data value equal to zero.
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L848A_A
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BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
PCI Configuration Space
Internal addressing of BT848 registers occurs via AD[7:2] and the byte enable bits of the PCI bus. The 8-bit byte-address for each of the following register locations is {AD[7:2], 00}. As a single-function device, BT848 ignores bits AD[10:8]. CardBus CIS Pointer and Subsystem ID/VendorID registers are not implemented in BT848. User-definable features, BIST, Cache Line Size, and Expansion ROM Base Address register are also not supported. The following types are used to specify how the BT848 registers are implemented: ROx: Read only with default value = x RW: Read/Write. All bits initialized to 0 at RST, unless otherwise stated. RW*: Same as RW, but data read may not be same as data written. RR: Same as RW, but writing a 1 resets corresponding bit location, writing 0 has no effect.
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L848A_A
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CONTROL REGISTER DEFINITIONS
PCI Configuration Registers
BT848/848A/849A
Single-Chip Video Capture for PCI
PCI Configuration Registers Vendor and Device ID Register
PCI Configuration Header Location 0x00
Bits [31:16] [15:0]
Type RO RO
Default 0x0350 0x351 0x109E
Name Device ID (BT848/848A) Device ID (Bt849A) Vendor ID (Brooktree)
Description Identifies the particular device or Part ID Code. Identifies manufacturer of device, assigned by the PCI SIG.
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BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Command and Status Register
Command and Status Register
PCI Configuration Header Location 0x04
The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a zero is written to this register, BT848 is logically disconnected from the PCI bus except for configuration cycles. The unused bits in this register are set to a logical zero. The Status[31:16] register is used to record status information regarding PCI bus related events.
Bits [31] [30] [29] [28] [27] [26:25] [24] Type RR RR RR RR RR RO RR Default 0 0 0 0 0 01 0 Name Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Address Decode Time Data Parity Reported Description Set when a parity error is detected, in the address or data, regardless of the Parity Error Response control bit. Set when SERR is asserted. Set when master transaction is terminated with Master Abort. Set when master transaction is terminated with Target Abort. Set when target terminates transaction with Target Abort. This occurs when detecting an address parity error. Responds with medium DEVSEL timing. A value of 1 indicates that the bus master asserted PERR during a read transaction or observed PERR asserted by target when writing data to target. The Parity Error Response bit in the command register must have been enabled. Target capable of fast back-to-back transactions. A value of 1 enables the SERR driver. A value of 1 enables parity error reporting. A value of 1 enables BT848 to act as a bus initiator. A value of 1 enables response to Memory space accesses (target decode to memory mapped registers).
[23] [8] [6] [2] [1]
RO RW RW RW RW
1 0 0 0 0
FB2B Capable SERR enable Parity Error Response Bus Master Memory Space
L848A_A
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CONTROL REGISTER DEFINITIONS
Revision ID and Class Code Register
BT848/848A/849A
Single-Chip Video Capture for PCI
Revision ID and Class Code Register
PCI Configuration Header Location 0x08
Bits [31:8] [7:0]
Type RO RO
Default 0x040000 0x0X
Name Class Code Revision ID
Description BT848 is a multimedia video device. This register identifies the device revision.
Latency Timer Register
PCI Configuration Header Location 0x0C
Bits [15:8]
Type RW
Default 0x00
Name Latency Timer
Description The number of PCI bus clocks for the latency timer used by the bus master. Once the latency expires, the master must initiate transaction termination as soon as GNT is removed.
Note that bits [23:16] do return 0x00 indicating BT848 is a single-function device and implements header type 0.
Base Address 0 Register
PCI Configuration Header Location 0x10
Bits [31:12]
Type RW
Default Assigned by CPU at boot-up 0x008
Name Relocatable memory pointer Memory usage specification
Description Determine the location of the registers in the 32-bit addressable memory space. Reserve 4 KB of memory-mapped address space for local registers. Address space is prefetchable without side effects.
[11:0]
RO
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L848A_A
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
PCI Configuration Header Location 0x3C
Bits [31:25] [24:16]
Type RO RO
Default 0x28 0x10
Name Max_Lat Min_Gnt
Description Require bus access every 8.5 S, at a minimum, in units of 250nS. Affects the desired settings for the latency timer value. Desire a minimum grant burst period of 4 S to empty data FIFO, in units of 250nS. Affects the desired settings for the latency timer value. Set for 128 dwords, with 0 wait states. BT848 interrupt pin is connected to INTA, the only one usable by a single function device. The Interrupt Line register communicates interrupt line routing information between the POST code and the device driver. The POST code initializes this register with a value specifying to which input (IRQ) of the system interrupt controller the BT848 interrupt pin is connected. Device drivers can use this value to determine interrupt priority and vector information.
[15:8] [7:0]
RO RW
0x01
Interrupt Pin Interrupt Line
Min_Gnt and Max_Lat values are dependent on target performance (TRDY) and video mode (scale factors and color format). These values were chosen for best case target (0 wait-state) and worst-case video delivery (full-resolution 32-bit RGB).
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CONTROL REGISTER DEFINITIONS
Local Registers
BT848/848A/849A
Single-Chip Video Capture for PCI
Local Registers
BT848's local registers reside in the 4KB memory addressed space. All of the registers correspond to dwords or a subset thereof. The local registers may be written to or read through the PCI bus at any time. Internal addressing of the BT848 local registers occurs via AD[11:2] and the byte enable bits of the PCI bus. The 8-bit byte-address for each of the following register locations is {AD[11:2], 0x00}. Any register may be written or read by any combination of the byte enables. The data to/from the video decoder/scaler registers and VDFC will come from PCI byte lane 0 (AD[7:0]) only. If the upper byte lanes are enabled for reading, the data returned is zero. Thus each register is separated by a byte address offset of four. All non-used addresses are reserved locations and return an undefined value. The scaling function needs to be controlled on a field basis to allow for different size/scaled images for preview and capture applications. All registers that affect scaling, translation, and capture on the input side of the FIFO provide for even and odd field values that switch automatically on the internal FIELD signal.
NOTE:
Pins with alternate definitions on the BT848A/849A are indicated by shading.
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BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Device Status Register
Device Status Register
Memory Mapped Location 0x000 - (DSTATUS)
Upon reset it is initialized to 0x00. COF is the least significant bit. The COF and LOF status bits hold their values until reset to their default values by writing to them. The other six bits do not hold their values, but continually output the status.
Bits [7] Type RW Default 0 Name PRES Description Video Present Status. Video is determined as not present when an input sync is not detected in 31 consecutive line periods. 0 = Video not present. 1 = Video present. Device in H-lock. If HSYNC is found within 1 clock cycle of the expected position of HSYNC for 32 consecutive lines, this bit is set to a logical 1. Once set, if HSYNC is not found within 1 clock cycle of the expected position of HSYNC for 32 consecutive lines, this bit is set to a logical 0. 0 = Device not in H-lock. 1 = Device in H-lock. Field Status. This bit reflects whether an odd or even field is being decoded. 0 = Odd field. 1 = Even field. This bit identifies the number of lines found in the video stream. This bit is used to determine the type of video input to the BT848. Thirty-two consecutive fields with the same number of lines is required before this status bit will change. 0 = 525 line format (NTSC / PAL-M). 1 = 625 line format (PAL / SECAM). Crystal Select. This bit identifies which crystal port is selected. 0 = XTAL0 input selected. 1 = XTAL1 input selected. This bit must be set to zero. A logical one indicates the PLL is out of lock. Once s/w has initialized the PLL to run at the desired frequency, this bit should be read and cleared until it is no longer set (up to 100 ms). Then the clock input mode should be switched from xtal to PLL. Luma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow occurs, the bit is set to a logical 1. It is reset after being written to or a chip reset occurs. Chroma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow occurs, the bit is set to a logical 1. It is reset after being written to or a chip reset occurs.
[6]
RW
0
HLOC
[5]
RW
0
FIELD
[4]
RW
0
NUML
[3]
RW
0
CSEL
[2]
RW
0
Reserved PLOCK
[1]
RW
0
LOF
[0]
RW
0
COF
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CONTROL REGISTER DEFINITIONS
Input Format Register
BT848/848A/849A
Single-Chip Video Capture for PCI
Input Format Register
Memory Mapped Location 0x004 - (IFORM)
Upon reset it is initialized to 0x58. FORMAT(0) is the least significant bit.
Bits [7] [6:5] Type RW RW Default 0 10 Name Reserved MUXSEL Description This bit must be set to zero. Used for software control of video input selection. The BT848 can select between three composite video sources, or two composite and one S-video source. 00 = Reserved 01 = Select MUX2 input to MUXOUT 10 = Select MUX0 input to MUXOUT 11 = Select MUX1 input to MUXOUT 00 = Select MUX3 input to MUXOUT
MUXSEL [4:3] RW 11 XTSEL
If automatic format detection is required, logical 11 must be loaded. Logical 01 and 10 are used if software format selection is desired. 00 = Reserved 01 = Select XT0 input (only XT0 present) 10 = Select XT1 input (both XTs present) 11 = Auto XT select enabled (both XTs present) Automatic format detection may be enabled or disabled. The NUML bit is used to determine the input format when automatic format detection is enabled. 000 = Auto format detect enabled 001 = NTSC (M) input format 010 = NTSC w/o pedestal (Japan) 011 = PAL (B, D, G, H, I) input format 100 = PAL (M) input format 101 = PAL (N) input format 110 = SECAM input format 111 = Reserved 111 = PAL (N-combination) input format
[2:0]
RW
000
FORMAT
FORMAT
92
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Temporal Decimation Register
Temporal Decimation Register
Memory Mapped Location 0x008 - (TDEC)
Upon reset it is initialized to 0x00. DEC_RAT(0) is the least significant bit. This register enables temporal decimation by discarding a finite number of fields or frames from the incoming video.
Bits [7] Type RW Default 0 Name DEC_FIELD Description Defines whether decimation is by fields or frames. 0 = Decimate frames. 1 = Decimate fields. This bit aligns the start of decimation with an even or odd field. 0 = Start decimation on the odd field (an odd field is the first field dropped). 1 = Start decimation on the even field (an even field is the first field dropped). DEC_RAT is the number of fields or frames dropped out of 60 (NTSC) or 50 (PAL/SECAM) fields or frames. 0x00 value disables decimation (all video frames and fields are output).
[6]
RW
0
FLDALIGN
[5:0]
RW
000000
DEC_RAT
MSB Cropping Register
Memory Mapped Location 0x00C - Even Field (E_CROP) Memory Mapped Location 0x08C - Odd Field (O_CROP)
Upon reset it is initialized to 0x12. HACTIVE_MSB(0) is the least significant bit. See the VACTIVE, VDELAY, HACTIVE and HDELAY registers for descriptions on the operation of this register.
Bits [7:6] [5:4] [3:2] [1:0] Type RW RW RW RW Default 00 01 00 10 Name VDELAY_MSB(1) VACTIVE_MSB HDELAY_MSB HACTIVE_MSB Description The most significant two bits of vertical delay register. The most significant two bits of vertical active register. The most significant two bits of horizontal delay register. The most significant two bits of horizontal active register.
Notes: (1). For VDELAY_MSB the E_CROP and O_CROP address pointer is flipped. To write to the even field, VDELAY_MSB bits use the odd field address. To write to the odd field, VDELAY_MSB bits use the even field address.
Brooktree
(R)
L848A_A
93
CONTROL REGISTER DEFINITIONS
Vertical Delay Register, Lower Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Vertical Delay Register, Lower Byte
Memory Mapped Location 0x010 - Even Field (E_VDELAY_LO) Memory Mapped Location 0x090 - Odd Field (O_VDELAY_LO)
Upon reset it is initialized to 0x16. VDELAY_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit VDELAY register. The two MSBs of VDELAY are contained in the CROP register. VDELAY defines the number of half lines between the trailing edge of VRESET and the start of active video.
Bits [7:0] Type RW Default 0x16 Name VDELAY_LO Description The least significant byte of the vertical delay register.
Vertical Active Register, Lower Byte
Memory Mapped Location 0x014 - Even Field (E_VACTIVE_LO) Memory Mapped Location 0x094 - Odd Field (O_VACTIVE_LO)
Upon reset it is initialized to 0xE0. VACTIVE_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit VACTIVE register. The two MSBs of VACTIVE are contained in the CROP register. VACTIVE defines the number of lines used in the vertical scaling process.
Bits [7:0] Type RW Default 0xE0 Name VACTIVE_LO Description The least significant byte of the vertical active register.
Horizontal Delay Register, Lower Byte
Memory Mapped Location 0x018 - Even Field (E_DELAY_LO) Memory Mapped Location 0x098 - Odd Field (O_DELAY_LO)
Upon reset it is initialized to 0x78. HDELAY_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit HDELAY register. The two MSBs of HDELAY are contained in the CROP register. HDELAY defines the number of scaled pixels between the falling edge of HRESET and the start of active video.
Bits [7:0] Type RW Default 0x78 Name HDELAY_LO Description The least significant byte of the horizontal delay register. HACTIVE pixels will be output by the chip starting at the fall of HRESET.
94
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Horizontal Active Register, Lower Byte
Horizontal Active Register, Lower Byte
Memory Mapped Location 0x01C - Even Field (E_HACTIVE_LO) Memory Mapped Location 0x09C - Odd Field (O_HACTIVE_LO)
Upon reset it is initialized to 0x80. HACTIVE_LO(0) is the least significant bit. HACTIVE defines the number of horizontal active pixels per line output by the BT848. This 8-bit register is the lower byte of the 10-bit HACTIVE register. The two MSBs of HACTIVE are contained in the CROP register.
Bits [7:0] Type RW Default 0x80 Name HACTIVE_LO Description The least significant byte of the horizontal active register.
Horizontal Scaling Register, Upper Byte
Memory Mapped Location 0x020 - Even Field (E_HSCALE_HI) Memory Mapped Location 0x0A0 - Odd Field (O_HSCALE_HI)
Upon reset it is initialized to 0x02. This 8-bit register is the upper byte of the 16-bit HSCALE register.
Bits [7:0] Type RW Default 0x02 Name HSCALE_HI Description The most significant byte of the horizontal scaling ratio.
Horizontal Scaling Register, Lower Byte
Memory Mapped Location 0x024 - Even Field (E_HSCALE_LO) Memory Mapped Location 0x0A4 - Odd Field (O_HSCALE_LO)
Upon reset it is initialized to 0xAC. This 8-bit register is the lower byte of the 16-bit HSCALE register.
Bits [7:0] Type RW Default 0xAC Name HSCALE_LO Description The least significant byte of the horizontal scaling ratio.
Brooktree
(R)
L848A_A
95
CONTROL REGISTER DEFINITIONS
Brightness Control Register
BT848/848A/849A
Single-Chip Video Capture for PCI
Brightness Control Register
Memory Mapped Location 0x028 - (BRIGHT)
Upon reset it is initialized to 0x00.
Bits [7:0]
Type RW
Default 0x00
Name BRIGHT
Description The brightness control involves the addition of a two's complement number to the luma channel. Brightness can be adjusted in 255 steps, from -128 to +127. The resolution of brightness change is one LSB (0.39% with respect to the full luma range).
BRIGHT Brightness Changed By Hex Value Binary Value Number of LSBs -128 -127 . . -01 00 +01 . . +126 +127 +49.2% +49.6% -0.39% 0% +0.39% Percent of Full Scale -50% -49.6%
0x80 0x81 . . 0xFF 0x00* 0x01 . . 0x7E 0x7F
1000 0000 1000 0001 . . 1111 1111 0000 0000* 0000 0001 . . 0111 1110 0111 1111
96
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Miscellaneous Control Register
Miscellaneous Control Register
Memory Mapped Location 0x02C - Even Field (E_CONTROL) Memory Mapped Location 0x0AC - Odd Field (O_CONTROL)
Upon reset it is initialized to 0x20. SAT_V_MSB is the least significant bit.
Bits [7] Type RW Default 0 Name LNOTCH Description This bit is used to include the luma notch filter. For monochrome video, the notch filter should not be used. This will output full bandwidth luminance. 0 = Enable the luma notch filter 1 = Disable the luma notch filter When COMP is set to logical one, the luma notch is disabled. When COMP is set to logical zero, the C ADC is disabled. 0 = Composite Video 1 = Y/C Component Video The luma decimation filter is used to reduce the high-frequency component of the luma signal. Useful when scaling to CIF resolutions or lower. 0 = Enable luma decimation using selectable H filter 1 = Disable luma decimation This bit controls whether the first pixel of a line is a Cb pixel or a Cr pixel. For example, if CBSENSE is low and HDELAY is an even number, the first active pixel output is a Cb pixel. If HDELAY is odd, CBSENSE may be programmed high to produce a Cb pixel as the first active pixel output. 0 = Normal Cb, Cr order 1 = Invert Cb, Cr order This bit should only be written with a logical zero. The most significant bit of the luma gain (contrast) value. The most significant bit of the chroma (u) gain value. The most significant bit of the chroma (v) gain value.
[6]
RW
0
COMP
[5]
RW
1
LDEC
[4]
RW
0
CBSENSE
[3] [2] [1] [0]
RW RW RW RW
0 0 0 0
Reserved CON_MSB SAT_U_MSB SAT_V_MSB
Brooktree
(R)
L848A_A
97
CONTROL REGISTER DEFINITIONS
Luma Gain Register, Lower Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Luma Gain Register, Lower Byte
Memory Mapped Location 0x030 - (CONTRAST_LO)
Upon reset it is initialized to 0xD8. CONTRAST_LO(0) is the least significant bit.
Bits [7:0] Type RW Default 0xD8 Name CONTRAST_LO Description The CON_L_MSB bit and the CONTRAST_LO register concatenate to form the 9-bit CONTRAST register. The value in this register is multiplied by the luminance value to provide contrast adjustment.
CONTRAST
The least significant byte of the luma gain (contrast) value.
Decimal Value 511 510 . . 217 216 . . 128 . . 1 0 Hex Value 0x1FF 0x1FE . . 0x0D9 0x0D8* . . 0x080 . . 0x001 0x000 % of Original Signal 236.57% 236.13% . . 100.46% 100.00% . . 59.26% . . 0.46% 0.00%
98
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Chroma (U) Gain Register, Lower Byte
Chroma (U) Gain Register, Lower Byte
Memory Mapped Location 0x034 - (SAT_U_LO)
Upon reset it is initialized to 0xFE. SAT_U_LO(0) is the least significant bit. SAT_U_MSB in the CONTROL register, and SAT_U_LO concatenate to give a 9-bit register (SAT_U).
Bits [7:0] Type RW Default 0xFE Name SAT_U_LO Description This register is used to add a gain adjustment to the U component of the video signal. By adjusting the U and V color components of the video stream by the same incremental value, the saturation is adjusted.
SAT_U Decimal Value 511 510 . . 255 254 . . 128 . . 1 0 Hex Value 0x1FF 0x1FE . . 0x0FF 0x0FE* . . 0x080 . . 0x001 0x000 % of Original Signal 201.18% 200.79% . . 100.39% 100.00% . . 50.39% . . 0.39% 0.00%
Brooktree
(R)
L848A_A
99
CONTROL REGISTER DEFINITIONS
Chroma (V) Gain Register, Lower Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Chroma (V) Gain Register, Lower Byte
Memory Mapped Location 0x038 - (SAT_V_LO)
Upon reset it is initialized to 0xB4. SAT_V_LO(0) is the least significant bit. SAT_V_MSB in the CONTROL register and SAT_V_LO concatenate to give a 9-bit register (SAT_V).
Bits [7:0] Type RW Default 0xB4 Name SAT_V_LO Description This register is used to add a gain adjustment to the V component of the video signal. By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted.
SAT_V Decimal Value 511 510 . . 181 180 . . 128 . . 1 0 Hex Value 0x1FF 0x1FE . . 0x0B5 0x0B4* . . 0x080 . . 0x001 0x000 % of Original Signal 283.89% 283.33% . . 100.56% 100.00% . . 71.11% . . 0.56% 0.00%
100
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Hue Control Register
Hue Control Register
Memory Mapped Location 0x03C - (HUE)
Upon reset it is initialized to 0x00. HUE(0) is the least significant bit. An asterisk indicates the default option.
Bits [7:0] Type RW Default 0x00 Name HUE Description Hue adjustment involves the addition of a two's complement number to the demodulating subcarrier phase. Hue can be adjusted in 256 steps in the range -90 to +89.3, in increments of 0.7.
HUE Hex Value Binary Value Subcarrier Reference Changed By -90 -89.3 . . -0.7 00 +0.7 . . +88.6 +89.3 Resulting Hue Changed By +90 +89.3 . . +0.7 00 -0.7 . . -88.6 -89.3
0x80 0x81 . . 0xFF 0x00* 0x01 . . 0x7E 0x7F
1000 0000 1000 0001 . . 1111 1111 0000 0000* 0000 0001 . . 0111 1110 0111 1111
Brooktree
(R)
L848A_A
101
CONTROL REGISTER DEFINITIONS
SC Loop Control Register
BT848/848A/849A
Single-Chip Video Capture for PCI
SC Loop Control Register
Memory Mapped Location 0x040 - Even Field (E_SCLOOP) Memory Mapped Location 0x0C0 - Odd Field (O_SCLOOP)
Upon reset it is initialized to 0x00. Reserved(0) is the least significant bit.
Bits [7] Type RW Default 0 Name Reserved PEAK Description Reserved for future use. Must be written with a zero. This bit determines if the normal luma low pass filters are implemented via the HFILT bits or if the peaking filters are implemented. 0 = Normal luma low pass filtering 1 = Use luma peaking filters This bit controls the Chroma AGC function. When enabled, Chroma AGC will compensate for non-standard chroma levels. The compensation is achieved by multiplying the incoming chroma signal by a value in the range of 0.5 to 2.0. 0 = Chroma AGC Disabled 1 = Chroma AGC Enabled This bit determines whether the low color detector and removal circuitry is enabled. 0 = Low Color Detection and Removal Disabled 1 = Low Color Detection and Removal Enabled These bits control the configuration of the optional 6-tap Horizontal Low-Pass Filter. The auto-format mode determines the appropriate low-pass filter based on the horizontal scaling ratio selected. The LDEC bit in the CONTROL register must be programmed to zero to use these filters. 00* = Auto Format. If auto format is selected when horizontally scaling between full resolution and half resolution, no filtering is selected. When scaling between one-half and one-quarter resolution, the CIF filter is used. When scaling between one-quarter and one-eighth resolution, the QCIF filter is used, and at less than one-eight resolution, the ICON filter is used. 01 = CIF 10 = QCIF 11 = ICON If the PEAK bit is set to logical one, the HFILT bits determine which peaking filter is selected. 01 = Minimum peaking 10 = Medium peaking 11 = Maximum peaking These bits must be set to zero.
[6]
RW
0
CAGC
[5]
RW
0
CKILL
[4:3]
RW
00
HFILT
HFILT
[2:0]
RW
00
Reserved
102
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Output Format Register
Output Format Register
Memory Mapped Location 0x048 - (OFORM)
Upon reset it is initialized to 0x00. OFORM(0) is the least significant bit.
Bits [7] Type RW Default 0 Name RANGE Description Luma Output Range: This bit determines the range for the luminance output on the BT848. The range must be limited when using the control codes as video timing. 0 = Normal operation (Luma range 16-253, chroma range 2-253). Y=16 is black (pedestal). Cr, Cb=128 is zero color information. 1 = Full-range Output (Luma range 0-255, chroma range 2-253) Y=0 is black (pedestal). Cr, Cb=128 is zero color information. Luma Coring: These bits control the coring value used by the BT848. When coring is active and the total luminance level is below the limit programmed into these bits, the luminance signal is truncated to zero. 00 = 0 no coring 01 = 8 10 = 16 11 = 32 These bits must be set to zero.
[6:5]
RW
00
CORE
[4:0]
RW
00000
Reserved
Brooktree
(R)
L848A_A
103
CONTROL REGISTER DEFINITIONS
Vertical Scaling Register, Upper Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Vertical Scaling Register, Upper Byte
Memory Mapped Location 0x04C - Even Field (E_VSCALE_HI) Memory Mapped Location 0x0CC - Odd Field (O_VSCALE_HI)
Upon reset it is initialized to 0x60.
Bits [7] Type RW Default 0 Name YCOMB Description Luma Comb Enable: When enabled, the luma comb filter performs a weighted average on 2, 3, 4, or 5 lines of luminance data. The coefficients used for the average are fixed and no interpolation is performed. When disabled by a logical zero, filtering and full vertical interpolation is performed based upon the value programmed into the VSCALE register. 0* = Vertical low-pass filtering and vertical interpolation 1 = Vertical low-pass filtering only Chroma Comb Enable: This bit determines if the chroma comb is included in the data path. If enabled, a full line store is used to average adjacent lines of color information, reducing cross-color artifacts. 0 = Chroma comb disabled 1* = Chroma comb enabled Interlace: This bit is programmed to indicate if the incoming video is interlaced or non-interlaced. For example, if using the full frame as input for vertical scaling, this bit should be programmed high. If using a single field for vertical scaling, this bit should be programmed low. 0 = Non-interlace VS 1* = Interlace VS Vertical Scaling Ratio: These five bits represent the most significant portion of the 13-bit vertical scaling ratio register.
[6]
RW
1
COMB
[5]
RW
1
INT
[4:0]
RW
00000
VSCALE_HI
Vertical Scaling Register, Lower Byte
Memory Mapped Location 0x050 - Even Field (E_VSCALE_LO) Memory Mapped Location 0x0D0 - Odd Field (O_VSCALE_LO)
Upon reset it is initialized to 0x00.
Bits [7:0] Type RW Default 0x00 Name VSCALE_LO Description Vertical Scaling Ratio: These eight bits represent the least significant byte of the 13-bit vertical scaling ratio register. They are concatenated with five bits in VSCALE_HI. The following equation should be used to determine the value for this register: VSCALE = ( 0x10000 - { [ ( scaling_ratio ) - 1] * 512 } ) & 0x1FFF
104
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Test Control Register
Test Control Register
Memory Mapped Location 0x054 - (TEST)
This control register is reserved for putting the part into test mode. Write operation to this register may cause undetermined behavior and should not be attempted. A read cycle from this register returns 0x01, and only a write of 0x01 is permitted.
AGC Delay Register
Memory Mapped Location 0x060 - (ADELAY)
Upon reset, it is initialized to 0x68.
Bits [7:0] Type RW Default 0x68 Name ADELAY Description AGC gate delay for back-porch sampling. The following equation should be used to determine the value for this register: ADELAY = ( 6.8 S * 4*Fsc) + 7 Example for an NTSC input signal: ADELAY = (6.8 S x 14.32 MHz) + 7 = 104 (0x68)
Burst Delay Register
Memory Mapped Location 0x064 - (BDELAY)
Upon reset, it is initialized to 0x5D. BDELAY(0) is the least significant bit.
Bits [7:0] Type RW Default 0x5D Name BDELAY Description The burst gate delay for sub-carrier sampling. The following equation should be used to determine the value for this register: BDELAY = ( 6.5 S * 4*Fsc) Example for an NTSC input signal: BDELAY = (6.5 S x 14.32 MHz) = 93 (0x5D)
Brooktree
(R)
L848A_A
105
CONTROL REGISTER DEFINITIONS
ADC Interface Register
BT848/848A/849A
Single-Chip Video Capture for PCI
ADC Interface Register
Memory Mapped Location 0x068 - (ADC)
Upon reset, it is initialized to 0x82. CRUSH is the least significant bit.
Bits [7:6] [5] Type RW RW Default 10 0 Name Reserved SYNC_T Description These bits should only be written with logical one and logical zero. This bit defines the voltage level below which the SYNC signal can be detected. 0 = Analog SYNCDET threshold high (~125 mV) 1 = Analog SYNCDET threshold low (~75 mV) This bit is reserved in the BT848A and Bt849A and must be set to zero. This bit controls the AGC function. If disabled REFOUT is not driven and an external reference voltage must be provided. If enabled, REFOUT is driven to control the A/D reference voltage. 0 = AGC Enabled 1 = AGC Disabled When this bit is at a logical one, the decoder clock is powered down, but the device registers are still accessible. Recovery time is approximately one second to return to capturing video. 0 = Normal Clock Operation 1 = Shut down the System Clock (Power Down) This bit enables putting the luma ADC in sleep mode. 0 = Normal Y ADC operation 1 = Sleep Y ADC operation This bit enables putting the chroma ADC in sleep mode. 0 = Normal C ADC operation 1 = Sleep C ADC operation When the CRUSH bit is high (adaptive AGC), the gain control mechanism monitors the A/D's for overflow conditions. If an overflow is detected, the REFOUT voltage is increased, which increases the input voltage range on the A/D's. 0 = Non-adaptive AGC 1 = Adaptive AGC
SYNC_T [4] RW 0 AGC_EN
[3]
RW
0
CLK_SLEEP
[2]
RW
0
Y_SLEEP
[1]
RW
1
C_SLEEP
[0]
RW
0
CRUSH
106
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Video Timing Control
Video Timing Control
Memory Mapped Location 0x6C - Even Field (E_VTC) Memory Mapped Location 0xEC - Odd Field (O_VTC)
Upon reset, it is initialized to 0x00. VFILT(0) is the least significant bit.
Bits [7] Type RW Default 0 Name HSFMT Description This bit selects between a single-pixel-wide HRESET and the standard 64-clock-wide HRESET. 0 = HRESET is 64 CLKx1 cycles wide 1 = HRESET is 1 pixel wide 1 = HRESET is 32 CLKx1 cycles wide
HSFMT [6:2] [1:0] RW RW 00000 00 Reserved VFILT
These bits should only be written with a logical zero. These bits control the number of taps in the Vertical Scaling Filter. The number of taps must be chosen in conjunction with the horizontal scale factor to ensure the needed data does not overflow the internal FIFO. If the YCOMB bit in the VSCALE_HI register is a logical one, the following settings and equations apply: 00* = 2-tap 01 10 11 = 3-tap = 4-tap = 5-tap 1 -1 -- ( 1 + Z ) See Note 1. 2 1 -1 -2 -- ( 1 + 2Z + Z ) See Note 2. 4 1 -1 -2 -3 -- ( 1 + 3Z + 3Z + Z ) See Note 3. 8 1 -1 -2 -3 -4 ----- ( 1 + 4Z + 6Z + 4Z + Z ) See Note 3. 16
If the YCOMB bit in the VSCALE_HI register is a logical zero, the following settings and equations apply: 00* = 2-tap interpolation only. See Note 1. 01 10 11 = 2-tap = 3-tap = 4-tap 1 -1 -- ( 1 + Z ) and 2-tap interpolation. See Note 2. 2 1 -1 -2 -- ( 1 + 2Z + Z ) and 2-tap interpolation. See Note 3. 4 1 -1 -2 -3 -- ( 1 + 3Z + 3Z + Z ) and 2-tap interpolation. 8 See Note 3.
Note 1: Available at all resolutions. Note 2: Only available if scaling to less than 385 horizontal active pixels (CIF or smaller). Note 3: Only available if scaling to less than 193 horizontal active pixels (QCIF or smaller).
Brooktree
(R)
L848A_A
107
CONTROL REGISTER DEFINITIONS
Software Reset Register
BT848/848A/849A
Single-Chip Video Capture for PCI
Software Reset Register
Memory Mapped Location 0x07C - (SRESET)
This command register can be written at any time. Read cycles to this register return an undefined value. A data write cycle to this register resets the video decoder and scaler registers of BT848 to the default state. Writing any data value into this address resets the device.
Color Format Register
Memory Mapped Location 0x0D4 - (COLOR_FMT)
Bits [7:4]
Type RW
Default 0000
Name COLOR_ODD
Description Odd Field Color Format 0000 = RGB32 0001 = RGB24 0010 = RGB16 0011 = RGB15 0100 = YUY2 4:2:2 0101 = BtYUV 4:1:1 0110 = Y8 0111 = RGB8 (Dithered) 1000 = YCrCb 4:2:2 Planar 1001 = YCrCb 4:1:1 Planar 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Raw 8X Data 1111 = Reserved Even Field Color Format 0000 = RGB32 0001 = RGB24 0010 = RGB16 0011 = RGB15 0100 = YUY2 4:2:2 0101 = BtYUV 4:1:1 0110 = Y8 0111 = RGB8 (Dithered) 1000 = YCrCb 4:2:2 Planar 1001 = YCrCb 4:1:1 Planar 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Raw 8X Data 1111 = Reserved
[3:0]
RW
0000
COLOR_EVEN
108
L848A_A
Brooktree
(R)
BT848/848A/849A
Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Color Control Register
Color Control Register
Memory Mapped Location 0x0D8 - (COLOR_CTL)
A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8] swapped with B0[7:0].
Bits [7] [6] [5] [4] Type RW RW RW RW Default 0 0 0 0 Name EXT_FRMRATE COLOR_BARS RGB_DED GAMMA Description When the GPIO port is in SPI-16 input mode then this bit supplies NTSC(0)/PAL(1) which selects the gamma ROM. A value of 1 enables a color bars pattern at the input of the VDFC block. A value of 0 enables error diffusion for RGB16/RGB15 modes. A value of 1 disables it. A value of 0 enables gamma correction removal. The inverse gamma correction factor of 2.2 or 2.8 is applied and auto-selected by the respective mode NTSC/PAL. A value of 1 disables gamma correction removal. WordSwap Odd Field. A value of 1 enables word swapping of data entering the FIFO. W2[31:16] swapped with W0[15:0] WordSwap Even Field. A value of 1 enables word swapping of data entering the FIFO. W2[31:16] swapped with W0[15:0] ByteSwap Odd Field. A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8] swapped with B0[7:0] ByteSwap Even Field. A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8] swapped with B0[7:0]
[3] [2] [1]
RW RW RW
0 0 0
WSWAP_ODD WSWAP_EVEN BSWAP_ODD
[0]
RW
0
BSWAP_EVEN
Brooktree
(R)
L848A_A
109
CONTROL REGISTER DEFINITIONS
Capture Control
BT848/848A/849A
Single-Chip Video Capture for PCI
Capture Control
Memory Mapped Location 0x0DC - (CAP_CTL)
Bits [7:5] [4] [3] [2] [1] [0]
Type RW RW RW RW RW RW
Default 000 0 0 0 0 0
Name Reserved DITH_FRAME CAPTURE_VBI_ODD CAPTURE_VBI_EVEN CAPTURE_ODD CAPTURE_EVEN
Description These bits should only be written with a logical zero. 0 1 = Dither matrix applied to consecutive lines in a field. = Full frame mode.
A value of 1 enables VBI data to be captured into the FIFO during the odd field. A value of 1 enables VBI data to be captured into the FIFO during the even field. A value of 1 enables odd capture, allows VDFC to write data to FIFOs during the odd field. A value of 1 enables even capture, allows VDFC to write data to FIFOs during the even field.
VBI Packet Size
Memory Mapped Location 0x0E0 - (VBI_PACK_SIZE)
Bits [7:0]
Type RW
Default 0x00
Name VBI_PKT_LO
Description Lower 8 bits for the number of raw data DWORDS (four 8-bit samples) to capture while in VBI capture mode.
VBI Packet Size / Delay
Memory Mapped Location 0x0E4 - (VBI_PACK_DEL)
Bits [7:2] [1] [0]
Type RW RW RW
Default 000000 0 0
Name VBI_HDELAY EXT_FRAME VBI_PKT_HI
Description The number of CLKx1's to delay from the trailing edge of HRESET before starting VBI line capture. A value of 1 extends the frame output capture region to include the 10 lines prior to the default VACTIVE region. Upper bit for the number of raw data DWORDS (four 8-bit samples) to capture while in VBI capture mode.
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Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
PLL Reference Multiplier - PLL_F_LO (BT848A/849A only)
PLL Reference Multiplier - PLL_F_LO (BT848A/849A only)
Memory Mapped Location - 0x0F0
Upon reset it is initialized to 00
Bits [7:0] Type RW Default 0x00 Name PLL_F_LO Description Lower byte of PLL Frequency register.
PLL Reference Multiplier - PLL_F_HI (BT848A/849A only)
Memory Mapped Location - 0x0F4
Upon reset it is initialized to 00
Bits [7:0] Type RW Default 0x00 Name PLL_F_HI Description Upper byte of PLL Frequency register
Integer- PLL-XCI (BT848A/849A only)
Memory Mapped Location - 0x0F8
Upon reset it is initialized to 00
Bits [5:0] [6] Type RW RW Default 000000 0 Name PLL_I PLL_C Description PLL_I input. Range 6-63. If set to 0x00, then the PLL sleeps. PLL VCO post-divider 0 = Use 6 for post-divider 1 = Use 4 for post-divider PLL Ref xtal pre-divider 0 = Use 1 for pre-divider 1 = Use 2 for pre-divider
[7]
RW
0
PLL_X
Field Capture Counter-(FCAP) (BT848A/849A only)
Memory Mapped Location - 0x0E8
Upon reset it is initialized to 00
Bits [7:0] Type RW(1) Default 0x00 Name FCNTR Description Counts Field transitions when any CAPTURE bit is set.
Notes: (1). Any write to this register resets the contents to zero.
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CONTROL REGISTER DEFINITIONS
Interrupt Status
BT848/848A/849A
Single-Chip Video Capture for PCI
Interrupt Status
Memory Mapped Location 0x100 - (INT_STAT)
This register provides status of pending interrupt conditions. To clear the interrupts, read this register, then write the same data back. A 1 in the write data clears the particular register bit. The interrupt /status bits can be polled at any time.
Bits [31:28] Type RO Default Name RISCS Description Set when RISC status set bits are set in the RISC instruction. Reset when RISC status reset bits are set. Status only, no interrupt. A value of 0 indicates the DMA controller is currently disabled. Status only, no interrupt.
[27] [26] [25]
RO RO RO
RISC_EN Reserved RACK
Set when I2C operation is completed successfully. Otherwise, if the receiver does not acknowledge, then this bit will be reset when I2CDONE is set. Status only, no interrupt. 0 = Odd field, 1 = Even field. Status only, no interrupt.
[24] [23:20] [19]
RO RO RR 0000 0
FIELD Reserved SCERR
Set when the DMA EOL sync counter overflows. This is a severe error which requires the software to restart the field capture process. Also set when SYNC codes do not match in the data/instruction streams. Set when the DMA controller detects a reserved/unused opcode in the instruction sequence, or reserved/unused sync status in a SYNC instruction. In general, this includes any detected RISC instruction error. Set whenever the initiator receives a MASTER or TARGET ABORT. Set when a data parity error is detected (Parity Error Response must be set) while the initiator is reading RISC instructions. RISC_ENABLE is reset by the target to stop the DMA immediately. Set when a parity error is detected on the PCI bus for any of the transactions, R/W, address/data phases, initiator/target, issued/sampled PERR regardless of the Parity Error Response bit. All parity errors are serious except for data written to display. FIFO Data Stream Resynchronization occurred. The number of pixels, lines, or modes passing through FIFO does not match RISC program expectations. Set when a pixel data FIFO overrun condition results in the master, terminating the transaction due to excessive target latency. Set when a pixel data FIFO overrun condition is being handled by dropping as many DWORDs as needed, indicating bus access latencies are long.
[18]
RR
0
OCERR
[17] [16]
RR RR
0 0
PABORT RIPERR
[15]
RR
0
PPERR
[14]
RR
0
FDSR
[13] [12]
RR RR
0 0
FTRGT FBUS
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Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
Interrupt Status
Bits [11] [10] [9] [8] [7:6] [5] [4] [3] [2] [1] [0]
Type RR RO RR RR RO RR RR RR RR RR RR
Default 0 0 0 0 0 0 0 0 0 0 0
Name RISCI Reserved GPINT I2CDONE Reserved VPRES HLOCK OFLOW HSYNC VSYNC FMTCHG
Description Set when the IRQ bit in the RISC instruction is set.
Set upon the programmable edge or level of the GPINTR pin. Set when an I2C read or write operation has completed.
Set when the analog video signal input changes from present to absent or vice versa. Set if the horizontal lock condition changes on incoming video. Set when an overflow is detected in the luma or chroma ADCs. Set when the analog input begins a new video line, or at the GPIO HRESET leading edge. Set when FIELD changes on the analog input or GPIO input. Set when a video format change is detected, i.e. the analog input changes from NTSC to PAL or vice versa.
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CONTROL REGISTER DEFINITIONS
Interrupt Mask
BT848/848A/849A
Single-Chip Video Capture for PCI
Interrupt Mask
Memory Mapped Location 0x104 - (INT_MASK)
Bits [22:0]
Type RW
Default 0x000000
Name
Description A value of 1 enables the interrupt bit. The bits correspond to the same bits in the Interrupt Status register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The PCI INTA is level sensitive. It remains asserted until the device driver clears or masks the pending request.
[23]
RW
0
ETBF
0= 1=
Normal operation Enable TritonI PCI controller compatibility.
RISC Program Counter
Memory Mapped Location 0x120 - (RISC_COUNT)
Bits [31:0]
Type RO
Default
Name RISC_PC
Description The current value of the RISC program counter. This may be slightly ahead of the current instruction due to pre-fetching instructions into the queue.
RISC Program Start Address
Memory Mapped Location 0x114 - (RISC_STRT_ADD)
Bits [31:0]
Type RW
Default 0x00000000
Name RISC_IPC
Description Base address for the RISC program. Standard 32-bit memory space byte address, although the software must DWORD align by setting the lowest two bits to 00. The DMA controller begins executing pixel instructions at this address when RISC_ENABLE is set, i.e. the RISC program counter is loaded with this pointer at the rising edge of RISC_ENABLE.
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Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
GPIO and DMA Control
GPIO and DMA Control
Memory Mapped Location 0x10C - (GPIO_DMA_CTL)
Bits [15]
Type RW
Default 0
Name GPINTC
Description A value of 0 selects the direct non-inv/inv input from GPINTR to go to the interrupt status register. A value of 1 selects the rising edge detect of the GPINTI programmed input. A value of 1 inverts the input from the GPINTR pin immediately after the input buffer. A value of 0 enables GPIO inputs to be registered upon the rising edge of GPWE. A value of 1 enables GPIO inputs to be registered upon the falling edge of GPWE. 00 01 10 11 = Normal GPIO port. See the GPIO section for overriding conditions. = Synchronous Pixel Interface output mode. = Synchronous Pixel Interface input mode. = Reserved.
[14] [13]
RW RW
0 0
GPINTI GPWEC
[12:11]
RW
00
GPIOMODE
[10]
RW
0
GPCLKMODE
A value of 1 enables CLKx1 to be output on GPCLK. A value of 0 disables the output and enables GPCLK to supply the internal pixel clock during SPI-16 input mode, otherwise this pin is assumed to be inactive. This bit should only be written with a logical zero. Planar mode trigger point for FIFO2 and FIFO3. 00 = 4 DWORDs 01 = 8 DWORDs 10 = 16 DWORDs 11 = 32 DWORDs Planar mode trigger point for FIFO1. 00 = 4 DWORDs 01 = 8 DWORDs 10 = 16 DWORDs 11 = 32 DWORDs Packed mode FIFO Trigger Point. The number of DWORDs in the FIFOs in total before the DMA controller begins to burst data onto the PCI bus. 00 = 4 DWORDs 01 = 8 DWORDs 10 = 16 DWORDs 11 = 32 DWORDs A value of 1 enables the DMA controller to process pixel dataflow instructions beginning at the RISC program start address. A value of 1 enables the data FIFO, while 0 flushes or resets it.
[9:8] [7:6]
RW RW
00 00
Reserved PLTP23
[5:4]
RW
00
PLTP1
[3:2]
RW
00
PKTP
[1] [0]
RW RW
0 0
RISC_ENABLE FIFO_ENABLE
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CONTROL REGISTER DEFINITIONS
GPIO Output Enable Control
BT848/848A/849A
Single-Chip Video Capture for PCI
GPIO Output Enable Control
Memory Mapped Location 0x118 - (GPIO_OUT_EN)
Bits [23:0]
Type RW
Default 0X000000
Name GPOE
Description Writes to this register provide data to the output buffer enables. A value of 1 enables the driver.
GPIO Registered Input Control
Memory Mapped Location 0x11C - (GPIO_REG_INP)
Bits [23:0]
Type RW
Default 0X000000
Name GPIE
Description Writes to this register provide data to the mux selects on the input buffers. A value of 0 selects the direct input data to be read for GPDATA. A value of 1 selects the registered input for GPDATA. Data on the GPIO pins is registered upon the programmable edge of GPWE.
GPIO Data I/O
Memory Mapped Location 0x200-0x2FF - (GPIO_DATA)
Bits [23:0]
Type RW
Default
Name GPDATA
Description Writes to this register provide data to the output buffers. Read data is from the input buffer. Data from this register can only be read if output enables are set and GPIOMODE is set to normal.
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Single-Chip Video Capture for PCI
CONTROL REGISTER DEFINITIONS
I2C Data/Control
I2C Data/Control
Memory Mapped Location 0x110
Bits [31:24] [23:16] [15:8]
Type RW RW RW
Default
Name I2CDB0 I2CDB1 I2CDB2
Description First byte sent in an I2C transaction. Typically this will be the base or chip 7-bit address and the R/W bit. Second byte sent in an I2C write transaction, usually a sub-address. Third byte sent in an I2C write transaction, usually the data byte. After a read transaction, this byte register will contain the data read from the slave. Programmable divider after PCI clock/16 for SDA/SCL bit stream generation. This value must be set to zero for software mode. A value of 1 enables bit-level clock synchronization which allows the slave to insert wait states. A value of 0 indicates a write transaction is to consist of sending two bytes I2CDB(0-1), while a value of 1 indicates a 3-byte write transmission. A value of 1 releases the SCL output, and a 0 forces the SCL output low. This bit must be set to a 1 during hardware mode. This override is for direct software control of the bus. Reading this bit provides access to the buffered SCL input pin. A value of 1 releases the SDA output, and a 0 forces the SDA output low. This bit must be set to a 1 during hardware mode. This override is for direct software control of the bus. Reading this bit provides access to the buffered SDA input pin.
[7:4] [3] [2]
RW RW RW
00000 0 0
I2CDIV I2CSYNC I2CW3B
[1]
RW
1
I2CSCL
[0]
RW
1
I2CSDA
The data bytes can be read back after writing if I2CDIV is set to 0 (software drive mode). Otherwise, since the register will be in shift mode during I2C circuit mode, the read data will be different from the data written to the register. The data read from the slave will be stable after issuing a read slave transaction and I2CDONE is set.
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CONTROL REGISTER DEFINITIONS
I2C Data/Control
BT848/848A/849A
Single-Chip Video Capture for PCI
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CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
Introduction
The registers in this section are only required when using the GPIO port to input digital video signal. These registers are included to enable the GPIO port to seamlessly connect to digital video cameras.
Digital Video Signal Interface Format
Memory Mapped Location 0x0FC - (DVSIF)
Upon reset, it is initialized to 0x000.
Bits [2:0] Type RW Default 000 Name VSFMT Description 000 001 010 011 100 101 110 111 00 01 10 11 = ANALOG = CCIR65 = ByteStream = Reserved = External Hsync, VSYNC = External HSYNC, Field = Reserved = Reserved = HS/VS aligned with Cb = HS/VS aligned with Y0 = HS/VS aligned with Cr = HS/VS aligned with Y1
[4:3]
RW
SVREF
5
RW
VSIF_ESO
Enable Sync output for synchronizing video Input 1 = Syncs are outputs 0 = Syncs are inputs Enable bypass of chroma filters. Use when HSCALE is set to 0. 1 = Bypass chroma filters 0 = Use chroma filters Remap GPDATA [5:0] inputs from GPIO [5:0] to GPX [5:0] 1 = Remap outputs 0 = Outputs are the same as GPIO on the BT848
6
RW
VSIF_BCF
7
RW
GPX_EN
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CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
Timing Generator Load Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Timing Generator Load Byte
Memory Mapped Location 0x080 - (TGLB)
Upon reset, it is initialized to 00.
Bits [7:0] Type RW Default 00 Name TGLB Description Load SRAM 1 byte at a time, in sequence after a TGC_AR. Load the least significant byte first. Each write to this address causes an automatic advance of the SRAM byte location. Reading from this address only reads the current byte. The TGC_AI bit must be pulsed by s/w in order for the SRAM byte location to advance.
Timing Generator Control
Memory Mapped Location 0x084 - (TGCTRL)
Upon reset, it is initialized to 00.
Bits 0 Type RW Default 00 Name TGC_VM Description Timing Generator Video Mode enable. 0 = Read/write mode 1 = Enable timing generator/read mode Timing Generator Address Reset. Timing Generator Read Address Increment -active hi pulse increments the read address. Decoder Input Clock Select. 00 = Normal xtal 0/xtal 1 mode 01 = PLL 10 = GPCLK(1) 11 = GPCLK - inverted(1) GPCLK Output Clock Select 00 = CLKx1 01 = xtal 0 input 10 = PLL 11 = PLL - inverted Must be written with a logical zero.
1 2 [4:3]
RW RW RW
GPC_AR TGC_AI TGCKI
[6:5]
RW
TGCKO
7
-
Reserved
Notes: (1). Since the entire decoder will be running off the external clock GPCLK, when selecting the GPCLK is activated, the decoder functionality is subject to a halt condition if the input port is disconnected. A clock detect circuit will allow the decoder to fall back on either the PLL or the Xtal, whichever is enabled via PLL_I. If the PLL has been put to sleep, then the decoder will fall back on the Xtal0 input. The VPRES status condition indicates the status of the clock detect output when in digital video input mode which is monitoring GPCLK. Note that it is desirable for SW to set up the PLL to run at the same frequency as the GPCLK input, so if the digital camera is disconnected, then blue-field timing will run properly.
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Single-Chip Video Capture for PCI
CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
Luma Gain Register, Lower Byte
Luma Gain Register, Lower Byte
Memory Mapped Location 0x030 - (CONTRAST_LO)
This is the alternate definition for the CONTRAST_LO register when using the BT848A/849A. Upon reset it is initialized to 0xD8 (this must be changed to 0x80 to get standard contrast values when in digital video mode). The CONTRAST register when used in digital video input mode, requires different programming time contrast adjustments as in analog video decode operation.
Bits [7:0] Type RW Default 0xD8 Name CONTRAST_LO Description The CON_L_MSB bit and the CONTRAST_LO register concatenate to form the 9-bit CONTRAST register. The value in this register is multiplied by the luminance value to provide contrast adjustment.
CONTRAST_LO
The least significant byte of the luma gain (contrast) value.
Decimal Value 511 510 . . 217 216 . . 128 . . 1 0
NOTE:
Hex Value 0x1FF 0x1FE . . 0x0D9 0x0D8 . . 0x080 . . 0x001 0x000
% of Original Signal 399.22% 398.43% . . 169.53% 168.75% . . 100% . . 0.78% 0.00%
The BRIGHT function has the same register definition in the digital section as in the analog section. However, the Bright function does precede the CONTRAST function in the decoder signal processing sequence, therefore any brightness applied is also gained by the CONTRAST setting.
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CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
Chroma (V) Gain Register, Lower Byte
BT848/848A/849A
Single-Chip Video Capture for PCI
Chroma (V) Gain Register, Lower Byte
Memory Mapped Location 0x038 - (SAT_V_LO)
This is the alternate definition for the SAT_V_LO register when using the BT848A/849A. Upon reset it is initialized to 0xB4 (this must be changed to 0x80 to get standard chroma (V) gain values when in digital video mode). The SAT_V register when used in digital video input mode requires different programming to get the same V gain adjustments as in analog video decode operation.
Bits [7:0] Type RW Default 0xB4 Name SAT_V_LO Description This register is used to add a gain adjustment to the V component of the video signal. By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted.
SAT_V_LO Decimal Value 511 510 . . 255 254 . . 128 . . 1 0 Hex Value 0x1FF 0x1FE . . 0x0FF 0x0FE . . 0x080 . . 0x001 0x000 % of Original Signal 399.22% 398.43% . . 199.22% 198.44% . . 100% . . 0.78% 0.00%
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Single-Chip Video Capture for PCI
CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
Chroma (U) Gain Register, Lower Byte
Chroma (U) Gain Register, Lower Byte
Memory Mapped Location 0x034 - (SAT_U_LO)
This is the alternate definition for the SAT_U_LO register when using the BT848A/849A. Upon reset it is initialized to 0xFE (this must be changed to 0x80 to get standard chroma (U) gain values when in digital video mode). The SAT_U register when used in digital video input mode requires different programming to get the same U gain adjustments as in analog video decode operation.
Bits [7:0] Type RW Default 0xFE Name SAT_U_LO Description This register is used to add a gain adjustment to the U component of the video signal. By adjusting the U and V color components of the video stream by the same incremental value, the saturation is adjusted.
SAT_U_LO Decimal Value 511 510 . . 181 180 . . 128 . . 1 0
NOTE:
Hex Value 0x1FF 0x1FE . . 0x0B5 0x0B4 . . 0x080 . . 0x001 0x000
% of Original Signal 399.22% 398.43% . . 141.41% 140.63% . . 100% . . 0.78% 0.00%
The standard 100% settings are also different for SECAM vs NTSC or PAL.
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CONTROL REGISTER DIGITAL VIDEO IN SUPPORT (BT848A/849A ONLY)
HDELAY/HSCALE
BT848/848A/849A
Single-Chip Video Capture for PCI
HDELAY/HSCALE
HDELAY = 128 * (#DesiredPixels/#Hactive Pixels) HSCALE = 4096 * (#HactivePixels/#DesiredPixels -1)
This is the alternate usage for the HDELAY and HSCALE registers when using the BT848A/849A. The HSCALE function has not changed, but there are more #HactivePixels standard input formats to consider.Since overscan, underscan, or normal scan is a subjective requirement, the formula for horizontal scaling may need to be adjusted for each video input format or standard being implemented. HDELAY should be set to 128 (0x80) for most pixel formats when unscaled. However, HDELAY may need to be empirically determined for video input formats where the normal 0x80 and scaled derivatives do not correctly compensate for horizontal misalignment.
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PARAMETRIC INFORMATION
DC Electrical Parameters
Table 16. Recommended Operating Conditions Parameter Power Supply -- Analog Power Supply -- Digital Maximum |VDD - VAA| MUX0, MUX1, MUX2, and MUX3 Input Range (AC coupling required) YIN, CIN Amplitude Range (AC coupling required) Ambient Operating Temperature TA 0.5 0.5 0 1.00 1.00 Symbol VAA, VPOS VDD, VDDP, VDDG Min 4.75 4.75 Typ 5.00 5.00 Max 5.25 5.25 0.5 2.00 2.00 +70 Units V V V V V C
Table 17. Absolute Maximum Ratings Parameter VAA (measured to AGND) VDD (measured to GND) Voltage on any signal pin(1) Analog Input Voltage Ambient Operating Temperature Storage Temperature Junction Temperature Vapor Phase Soldering (15 Seconds) TA TS TJ TVSOL Symbol VAA, VPOS VDD, VDDP, VDDG DGND - 0.5 AGND - 0.5 0 -65 Min Max 7.00 7.00 VDD + 0.5 VAA + 0.5 +70 +150 +125 +220 Units V V V V C C C C
Notes: (1). Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V or drops below ground by more than 0.5 V can induce destructive latchup.
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PARAMETRIC INFORMATION
DC Electrical Parameters
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 18. DC Characteristics Parameter Digital Inputs PCI Inputs Input High Voltage (TTL) Input Low Voltage (TTL) GPIO/I2C Input High Voltage Input Low Voltage Input High Voltage (XT0I, XT1I) Input Low Voltage (XT0I, XT1I) Input High Current (VIn=2.7 V) Input Low Current (VIN=0.5 V) Input Capacitance (f=1 MHz, VIN=2.4 V) Digital Outputs PCI Outputs Output High Voltage (IOH = -2 mA) Output Low Voltage (IOL= 6 mA) GPIO/I2C Output High Voltage (IOH = -400 A) Output Low Voltage (IOL= 3.2 mA) 3-State Current Output Capacitance Analog Pin Input Capacitance Symbol Min Typ Max Units
VIH VIL VIH VIL VIH VIL IIH IIL CIN
2.0 -0.5 2.0 -0.5 3.5 GND - 0.5
VDDP + 0.5 0.8 VDDG + 0.5 0.8 VDDP + 0.5 1.5 70 -70 5
V V V V V V A A pF
VOH VOL VOH VOL IOZ CO CA
2.4
VDDP 0.55 VDDG 0.4 10 5 5
V V V V A pF pF
2.4
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PARAMETRIC INFORMATION
AC Electrical Parameters
AC Electrical Parameters
Table 19. Clock Timing Parameters Parameter NTSC: 8*FSC Rate (50 PPM source required) PAL: 8*FSC Rate (50 PPM source required) XT0 and XT1 Inputs: Cycle Time High Time Low Time Figure 42. Clock Timing Diagram
XT0I or XT1I 2 3 1
Symbol FS2 FS2 1 2 3
Min
Typ 28.636363 35.468950
Max
Units MHz MHz ns ns ns
28.2 12 12
Table 20. GPIO SPI Mode Timing Parameters Parameter NTSC: 4*FSC Rate PAL: 4*FSC Rate GPCLK Duty Cycle GPCLK (falling edge) to Data Delay Data/Control Setup to GPCLK (falling edge) Data/Control Hold to GPCLK (falling edge) GPCLK Input: Cycle Time Low Time High Time Figure 43. GPIO Timing Diagram Symbol FS1 FS1 4 5 6 7 8 9 45 0 5 5 56.4 24 24 Min Typ 14.318181 17.734475 55 15 Max Units MHz MHz % ns ns ns ns ns ns
GPCLK 8 SPI-Output Mode 4 Pixel and GPWE Data 9 7
SPI-Input and Digital VideoIn Mode
5 Pixel and GPWE Data
6
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PARAMETRIC INFORMATION
AC Electrical Parameters
BT848/848A/849A
Single-Chip Video Capture for PCI
Table 21. Power Supply Current Parameters Parameter Supply Current VAA=VDD=5.0V, FS2=28.64 MHz, T=25C VAA=VDD=5.25V, FS2=35.47 MHz, T=70C VAA=VDD=5.25V, FS2=35.47 MHz, T=0C Supply Current, Power Down Symbol I 220 262 280 50 mA mA mA mA Min Typ Max Units
Table 22. Power Supply Current Parameters (BT848A/849A only)
Supply Current VAA=VDD=5.0V, FS2=28.64 MHz, T=25C VAA=VDD=5.25V, FS2=35.47 MHz, T=70C VAA=VDD=5.25V, FS2=35.47 MHz, T=0C Supply Current, Power Down
I TBD TBD TBD TBD mA mA mA mA
Table 23. JTAG Timing Parameters Parameter TMS, TDI Setup Time TMS, TDI Hold Time TCK Asserted to TDO Valid TCK Asserted to TDO Driven TCK Negated to TDO Three-stated TCK Low Time TCK High TIme Symbol 10 11 12 13 14 15 16 Min Typ 10 10 41 11 115 25 25 Max Units ns ns ns ns ns ns ns
Figure 44. JTAG Timing Diagram 10 TDI, TMS 15 TCK 16 12 13 TDO 14 11
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Single-Chip Video Capture for PCI
PARAMETRIC INFORMATION
AC Electrical Parameters
Table 24. Decoder Performance Parameters Parameter Horizontal Lock Range Fsc, Lock-in Range Gain Range
NOTE:
Symbol
Min
Typ
Max 7
Units % of Line Length Hz
800 -6 6
dB
Test conditions (unless otherwise specified): "Recommended Operating Conditions." TTL input values are 0-3 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for digital inputs and outputs. Pixel and control data loads 30 pF and 10 pF. GPCLK load 50 pF. See PCI specification revision 2.1 for PCI timing parameters.
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PARAMETRIC INFORMATION
Package Mechanical Drawing
BT848/848A/849A
Single-Chip Video Capture for PCI
Package Mechanical Drawing
Figure 45. 160-pin PQFP Package Mechanical Drawing
Datasheet Revision History
Table 25. BT848 Datasheet Revision History Revision A Date 02/07/97 Description Initial Release
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Brooktree
(R)
Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707 (619) 452-7580 1(800) 2-BT-APPS FAX: (619) 452-1249 Internet: apps@brooktree.com L848A_A
printed on recycled paper

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Price & Availability of BT848

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